This manuscript presents an improved system research that can detect and recognize the person in 3D space automatically and without the interaction of the people's faces. This system is based not only on a quantum computation and measurements to extract the vector features in the phase of characterization but also on learning algorithm (using SVM) to classify and recognize the person. This research presents an improved technique for automatic 3D face recognition using anthropometric proportions and measurement to detect and extract the area of interest which is unaffected by facial expression. This approach is able to treat incomplete and noisy images and reject the non-facial areas automatically. Moreover, it can deal with the presence of holes in the meshed and textured 3D image. It is also stable against small translation and rotation of the face. All the experimental tests have been done with two 3D face datasets FRAV 3D and GAVAB. Therefore, the test's results of the proposed approach are promising because they showed that it is competitive comparable to similar approaches in terms of accuracy, robustness, and flexibility. It achieves a high recognition performance rate of 95.35% for faces with neutral and non-neutral expressions for the identification and 98.36% for the authentification with GAVAB and 100% with some gallery of FRAV 3D datasets.
Road sign recognition is part of the automatic driver assistance systems implemented on the dashboard of vehicles. The recognition task is often carried out based on a classification procedure manipulating the detected signs. Classification tasks can be resolved by the use of multilayer artificial neural network systems. This article proposes an optimized real-time on-chip hardware implementation of multilayer perceptron system used for road sign classification. Four architectural approaches were described: on the one hand, the classic and the serial optimized architectures that offer a very significant reduction in hardware resources, and, on the other hand, the parallel and the optimized architectures, which offer a much reduced, time execution. In order to benefit from the advantages of the allocated hardware resources and the classification of the runtime process, these four architectures have been implemented on field programmable gate array Virtex-6 devices and their performances were quantified and evaluated according to a cost criterion. The energy dissipated by each of these architectures was measured; the achieved results have allowed us to conclude that the serial optimized architecture is the optimal solution, since it creates a tradeoff between the low cost, and the energy efficiency, and still real-time for the considered application.
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