Real-time embedded system for traffic sign recognition based on ZedBoard

Farhat, Wajdi; Faiedh, Hassène; Souani, Chokri; Besbes, Kamel

doi:10.1007/s11554-017-0689-0

Cited by 23 publications

(16 citation statements)

References 39 publications

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“…Smart cameras are machine vision systems that, in addition to sensors that capture images, provide the capability of extracting application-specific information from captured images. These embedded systems equipped with camera sensors represent efficient on-board solutions for several commercial applications, ranging from Advanced Driver-Assistance Systems (ADAS) to automated surveillance systems [1,2]. Computer vision tasks that lie behind these applications are very computationally intensive, often requiring special-purpose solutions to ensure real-time performances and low-power dissipation.…”

Section: Introductionmentioning

confidence: 99%

“…However, in many applications, only the specific features produced by the FC computation are actually subsequently processed [1,7,8,9,10,11,12,13], which makes the intermediate output of the CCL step not strictly necessary. As an example, extracting the area of the connected components is fundamental in the medical field for classification of blood infections [7] and cancer detection [8,9], as well as for automotive [1] and space [12] applications. In these contexts, multiple image scans required to fully complete the CCL step can be avoided [14] and one-scan CCA algorithms can be exploited to achieve higher performances [15].…”

Section: Introductionmentioning

confidence: 99%

“…Hardware architectures for CCA computation are highly demanded in all application fields where high-speed, resource efficiency, and low-power consumption are mandatory constraints. Most often, they are adopted in modern design solutions where embedded systems equipped with high-resolution camera sensors are used to realize fast memory-efficient streamed-oriented systems [1,2].…”

Section: Introductionmentioning

confidence: 99%

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An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis

Spagnolo

Perri

Corsonello

2019

Sensors

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Connected Component Analysis (CCA) plays an important role in several image analysis and pattern recognition algorithms. Being one of the most time-consuming tasks in such applications, specific hardware accelerator for the CCA are highly desirable. As its main characteristic, the design of such an accelerator must be able to complete a run-time process of the input image frame without suspending the input streaming data-flow, by using a reasonable amount of hardware resources. This paper presents a new approach that allows virtually any feature of interest to be extracted in a single-pass from the input image frames. The proposed method has been validated by a proper system hardware implemented in a complete heterogeneous design, within a Xilinx Zynq-7000 Field Programmable Gate Array (FPGA) System on Chip (SoC) device. For processing 640 × 480 input image resolution, only 760 LUTs and 787 FFs were required. Moreover, a frame-rate of ~325 fps and a throughput of 95.37 Mp/s were achieved. When compared to several recent competitors, the proposed design exhibits the most favorable performance-resources trade-off.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis

Spagnolo

Perri

Corsonello

2019

Sensors

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“…The latter has the same size of the input image and contains the labels assigned to the input pixels.Several attempts to improve the performance of these algorithms were presented in the recent past. They exploit parallelism by means of either multi-core processors and Graphics Processing Units (GPUs) [5,[27][28][29][30][31] or custom hardware architectures [10,11,[14][15][16][17][18][19][20][21][22][23]26]. As it is well known, for many consumer applications, like those related to the Internet of things (IoT), reaching high speed is as important as achieving low cost and high energy efficiency [16,32].…”

mentioning

confidence: 99%

“…The main goal of the CCA is to extract, for the connected components (i.e., different objects) in an input image, some features that are subsequently processed depending on the specific application. One-scan CCA algorithms [1,2,6,9,10,15,17,21,24,26] are particularly efficient since they exploit a provisional CCL step to distinguish the different connected components in the input image. The latter is scanned in raster order, and each foreground pixel is labeled depending on its four or eight neighbors, thus Electronics 2020, 9, 292…”

mentioning

confidence: 99%

A Parallel Connected Component Labeling Architecture for Heterogeneous Systems-on-Chip

2020

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Connected component labeling is one of the most important processes for image analysis, image understanding, pattern recognition, and computer vision. It performs inherently sequential operations to scan a binary input image and to assign a unique label to all pixels of each object. This paper presents a novel hardware-oriented labeling approach able to process input pixels in parallel, thus speeding up the labeling task with respect to state-of-the-art competitors. For purposes of comparison with existing designs, several hardware implementations are characterized for different image sizes and realization platforms. The obtained results demonstrate that frame rates and resource efficiency significantly higher than existing counterparts are achieved. The proposed hardware architecture is purposely designed to comply with the fourth generation of the advanced extensible interface (AXI4) protocol and to store intermediate and final outputs within an off-chip memory. Therefore, it can be directly integrated as a custom accelerator in virtually any modern heterogeneous embedded system-on-chip (SoC). As an example, when integrated within the Xilinx Zynq-7000 X C7Z020 SoC, the novel design processes more than 1.9 pixels per clock cycle, thus furnishing more than 30 2k × 2k labeled frames per second by using 3688 Look-Up Tables (LUTs), 1415 Flip Flops (FFs), and 10 kb of on-chip memory.

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An FPGA‐based tool for supporting the design, modeling, and evaluation of hybrid object recognition systems on computer engineering courses

Guzmán‐Ramírez,

Garcia,

Pacheco

et al. 2024

Comp Applic In Engineering

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The field of computer vision is characterized by computationally intensive algorithms and techniques with strict real‐time requirements. Field programmable gate arrays (FPGAs) are based on a concurrent paradigm which allows the design of efficient hardware architectures and has positioned FPGAs as an ideal device for implementing compute‐intensive applications. For this reason, FPGA technology has had a great impact in areas such as computer vision, where one of the main objectives for researchers working in this field is to create efficient automatic object recognition systems. Therefore, the need to provide undergraduates with the necessary skills to design FPGA‐based object recognition systems is evident. With this aim in mind, it is essential that specialization courses related to the design of these systems include the required resources for the student to apply the theoretical knowledge in solving practical problems. In this article, we present a development tool designed to help students, teachers, and researchers during the design‐modeling‐implementation process of object recognition systems based on FPGAs. The proposed tool operates under a modular approach as this facilitates the working on any of the phases of a recognition system and it is considered as a hybrid because the other phases can be developed using a software language. An empirical evaluation involving undergraduates enrolled in a Computer Engineering program was conducted to create a hardware architecture for the DAISY descriptor that uses the homogeneous features of objects immersed in images to produce an efficient representation. By considering similar descriptors such as Scale‐Invariant Feature Transform (SIFT) and Histogram of Oriented Gradients (HOG), DAISY is computed by convolving orientation maps instead of using weighted sums of gradient norms, which offers the same kind of invariance at a lower computational cost for the dense case. The results obtained during such an evaluation indicated that students consider this FPGA‐based tool to be an alternative to receiving practical training on designing systems for solving problems related to the area of object recognition.

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Real-time embedded system for traffic sign recognition based on ZedBoard

Cited by 23 publications

References 39 publications

An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis

An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis

A Parallel Connected Component Labeling Architecture for Heterogeneous Systems-on-Chip

An FPGA‐based tool for supporting the design, modeling, and evaluation of hybrid object recognition systems on computer engineering courses

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