Interconnect features of W metal, recessed in an SiO2 dielectric, can be formed using a novel chemical‐mechanical polish process. Mechanical action, to continually disrupt a surface passivating film on W, and chemical action, to remove W, appear to be requirements for workability of the process. A trial process chemistry using a ferricyanide etchant is described. Removal of the W is discussed in terms of competition between an etching reaction which dissolves W and a passivation reaction to reform WO3 on the surface of the W. This novel processing technology is compared with earlier methods of fabricating metal interconnect structures.

Application of the chemical mechanical polishing of silicon dioxide used as the interlevel dielectric in the manufacture of VLSI chips has led to the development of a relatively simple process for fabrication of the device wiring on such chips. The polishing process is used to remove the interlevel dielectric from the tops of interconnect studs and produce a planarized surface ready for the next level of wiring. The characteristics of this polishing process were studied on both blanket films of oxide and on wafers with device topography. Empirical relationships were found, and the results applied to device manufacture, resulting in process simplification while increasing chip reliability and yield.

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Ammonia adsorptions desorption and decomposition to H 2 and N 2 has been studied on the flat (lll) and stepped (557)