Observation of system level DRAM operations can provide insights for developing improved reliability screens such as burn-in. We instrumented a dual rank 4GB RDIMM to probe command bus traffic from the memory controller to the DRAMs on a server mother board. Internal DRAM operating states are derived by analyzing the command bus traffic. Analysis showed that when the controller uses an open page policy with bank interleaving, the active idle state can become the dominant bias configuration in activated arrays. This result can be applied to the development of an efficient burn in stress.
The technology and design of a very dense high performance NMOS double poly 256K DRAM fabricated with full wafer 1X lithography is described.The cell storage capacitor is enhanced through the use of a self aligned N+ storage node which allows full charge capture in the cell without sacrificing packing density.The design employs a standard folded metal bit line. By combining small contacts in the cell with narrow metal bit lines, a typical bit line capacitance of 300 fF is realized. Improved performance is achieved through the use of a polycide layer made with tungsten silicide for the word lines and active devices. Both sputtered and CVD materials have been used. Typical clock delays are less than 8 ns and measured access times of 80 ns have been demonstrated. Minimum image sizes of 1.2 microns have been used on 2 mask levels. ARCHITECTURE AND CHARACTERISTICS:This 256K DRAM is organized as 64K by four. Figure 1 shows the architectural block diagram. The design utilizes 64 bits/ folded bit line. Two sets of row decoders are used in order to shorten the polycide word line. Bit lines are patterned with a metal lift-off technique that allows a minimum design line size of 1.5 microns, resulting in a bit line capacitance of 300 fF. The die size is 32.2 sq. mrn, with dimensions of 4.56 mm x 7 . 0 7 mm. The cell measures 5 8 sq. urn and has a typical capacitance of 46 fF. (SEMs of the cell are shown in figs. 2 and 3. ) A net signal of 200 mV has been calculated. The area of the capacitor typically represents 34% of the area of the cell. With the use of a Hi-C boron implant, a 16% increase in cell capacitance can be realized. Addresses are multiplexed, and timing is controlled by conventional RAS/CAS schemes. Performance of this part is enhanced by the low sheet resistance of the polycide and short channels. Figures 4 and 5 show the relative behavior of this part with operating conditions of 4.4 volts at 22 C as a function of I Cell Array I I Cell Array 1 I Cell Array I I Array I Figure 1 256K DRAM Block Dlagram 13.3
An 18Mb DRAM has been designed in a 3.34, 0.5-pm CMOS process. The array consists of four independent, self-contained 4.5Mb quadrants. The chip output configuration defaults to 1 Mb x 18 for optimization of wafer screen tests, while 3. 3 4 or 5. 0 4 operation is selected by choosing one of two M2 configurations. Selection of 2Mb x 9 or 1 Mb x 18 operation with the various address options, in extended data-out or fast-page mode, is accomplished by selective wire-bonding during module build. Laser fuses enable yield enhancement by substituting eight 512Kb array I/O slices for nine in each quadrant of the 18Mb array. This substitution is independent in each quadrant and results in 1 Mb x 16 operation with 2Mb x 8, 4Mb x 4, and 4Mb x 4 with any 4Mb independently selectable (4Mb x 4 w/4 CE). Input and control circuitry are designed such that performance margins are constant across output and functional configurations. The architecture also provides for "cut-downs" to 16Mb, 4.5Mb, and 4Mb chips with I/O and function as above.
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