This paper presents a fundamental study of a stress memorization technique ͑SMT͒, which utilizes a capping nitride dielectric film to enhance negative channel field-effect transistor ͑nFET͒ device performance. SMT strain engineering is highly compatible with current standard complementary metal oxide semiconductor processes without introducing substantial additional complexity. In this work, we report that SMT-strained nFET exhibits a higher transconductance G m_lin , which indicates strain-induced electron mobility enhancement. The nFET short channel effect is also improved by the SMT process. Improved V t roll-off characteristics manifest itself and are shown to result from retarded junction diffusion as indicated by secondary-ion mass microscopy analysis. Finally, this work demonstrates that when combined with a strained contact etch stop layer ͑CESL͒ technique, SMT provides additional strain beyond that provided by the CESL, which results in further improved nFET performance.
This paper compares and analyzes the strained negative channel field effect transistor ͑nFET͒ device performance and the channel mobility behavior obtained by the stress memorization technique ͑SMT͒ using two different types of nitride films. These nitride film properties and wafer bowing during SMT fabrication are investigated. The electrical properties of SMT strained nFET devices including current-voltage characteristics, transconductance, carrier mobility, and interface state ͑D it ͒ are also analyzed. Although SMT nitride strain can enhance electron mobility, it is critical to control the nitride properties and its hydrogen content to minimize electron mobility degradation due to interface-state generation. Thus, a simple view of the essential physics of mobility enhancement in SMT strained nFETs has been provided. Results in this work also provide guidance to further nFET performance enhancement in the ever-more challenging device targets of future technology generations.Historically, improvements in the performance of metal-oxidesemiconductor field-effect transistors ͑MOSFETs͒ have relied on the aggressive reduction of physical geometries as guided by physicsbased scaling rules. 1 However, the increase in channel impurity concentration and the raise in vertical field required to control the short channel effect ͑SCE͒ actually degrade the carrier mobility and transistor performance. As the industry approaches the physical limitations of the traditional scaling techniques, alternative approaches for improving device performance have become increasingly attractive. Among the most promising of these techniques is the production of high mobility silicon channel structures most commonly accomplished using strained silicon technology. Strained silicon technology has emerged as one of the leading approaches to enhance the performance of today's highly scaled semiconductor devices. This technology has been adopted in production since the 90 nm process node, 2 and apparently this technology will continue through future generations. The strain can be induced either uniaxially or biaxially and strongly depends on integration challenges and the ability to maintain and control enhancement in aggressively scaled devices.Many strained silicon approaches have thus been developed to enhance carrier mobility. 2-4 Among these emerging approaches, uniaxial strained silicon technologies have become the mainstream for electron and hole mobility improvement especially under high oxide electrical field conditions. 3,4 For instance, a highly tensile nitride capping layer integrated as a contact etch stop layer ͑CESL͒ has been greatly utilized in advanced MOSFET fabrication owing to the resulting uniaxially tensile mechanical stress created in the negative channel field effect transistor ͑nFET͒ channel and the resulting electron mobility enhancement. 5,6 Another novel channel strain enhancement technique utilizing nitride dielectric deposition, commonly known as stress memorization technique ͑SMT͒, was first proposed by Chen et al. ...
The impact of back channel leakage ͑BCL͒ is thoroughly investigated when scaling down partially depleted ͑PD͒ silicon-oninsulator ͑SOI͒ devices. Back channel voltage is introduced as an indicator for monitoring the behavior of BCL. In addition to front-gate devices, back-gate devices also suffer from short channel effect. Finally, BCL can be successfully suppressed by optimizing process parameters such as the Si remains, the well implant, and the SOI thickness.Silicon-on-insulator ͑SOI͒ complementary metal oxide semiconductor ͑CMOS͒ has been widely used in recent years for its better device performance and scalability. Partially depleted ͑PD͒ SOI has a similar device structure to a bulk device. As a consequence, PD SOI can be fabricated using a standard bulk CMOS process. SOI devices have better circuit performance and lower power consumption due to lower channel doping and smaller parasitic capacitances. However, PD SOI devices possess several unique behaviors that do not exist in bulk devices, such as kink effect, 1-3 self-heating effect, 4-6 history delay effect, 7,8 and pass-gate leakage. 9,10 As metaloxide-semiconductor field effect transistor ͑MOSFET͒ sizes are scaled down to the nanoscale regime, leakage current is one of the key challenges faced by designers when attempting to realize devices that provide high performance and high scalability. In PD SOI, there is an additional leakage component other than the common leakage currents of a bulk device, such as junction leakage, gate induced drain leakage, and Drain Induced Barrier Lowering ͑DIBL͒. This leakage component is called back channel leakage ͑BCL͒, which is the subthreshold leakage of a back channel MOSFET. Figure 1 shows the cross section of a PD SOI device with a front-gate channel and a back-gate channel. When the back-gate channel is not turned off properly, BCL can contribute an additional leakage current to the device, resulting in a higher off-state leakage current. Several previous studies are focused on radiation induced BCL. [11][12][13][14][15] It was reported that back-gate bias could suppress the BCL and reduce its impact on circuits. [16][17][18] Consequently, it is important to characterize the BCL behavior and develop a strategy to effectively suppress the BCL.In this paper, the BCL has been characterized by applying a back-gate bias. In the Characterization and Methodology section, we present a methodology for monitoring the BCL. The back-gate device also suffers from the short channel effect ͑SCE͒. In the Results and Discussion section, we discuss the methods used to minimize the BCL of p-MOSFET. Finally, the BCL can be fully controlled in a 45 nm PD SOI process by optimizing three key process parameters: Si remains, well dose, and SOI thickness. Characterization and MethodologyThe devices used in this study are fabricated using a 45 nm SOI process. 19 Figure 2 shows the Id-Vg curves for a p-MOS ͑W/L = 0.6/0.04 um͒ at different back-gate biases ranging from 0 to 30 V. A large subthreshold leakage current occurs when the back-gate ...
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