CMOS on dual SOI thickness for optimal performance

Introduction

“…As compared to the bulk silicon substrate, the architecture of SOI MOSFET is more flexible due to several parameters such as thicknesses of film and buried oxide, substrate doping, and back-gate bias which are used for optimization and scaling. The short-channel effect, junction capacitances, and doping fluctuation are mitigated in ultrathin SOI films [54,55]. The main advantage of SOI as compared to bulk silicon is its compatibility with the use of high resistivity substrates to reduce the substrate coupling and RF losses [56].…”

Trade-Off between Gate Oxide Integrity and Transistor Performance for FinFET Technology

“…ESiGe with high Ge concentration provides uniaxial stress to boost electron mobility, and in situ boron doped eSiGe with boron concentration great than 2e20 cm −3 reduces the contact resistance and source/drain resistance. [5][6][7][8] High-K/metal-gate (HK/MG) provides low gate leakage current while enabling the scaling of equivalent oxide thickness (EOT). [9][10][11] This work explores a new interaction between eSiGe junction and gate oxide integrity in FinFET technology.…”