Trade-Off between Gate Oxide Integrity and Transistor Performance for FinFET Technology

Abstract

This work reports that, for the first time, the engineering of eSiGe proximity and eSiGe layer-one (L1) thickness modulates gate oxide integrity and device performance simultaneously in the leading edge FinFET technology. It is observed that there is a tradeoff between the benefit of transistor performance and the cost of gate oxide breakdown voltage (Vbd) degradation. TEM analysis indicates that eSiGe L1 is exposed to interfacial-layer/high-K in replaced-metal-gate (RMG) processes, suggesting gate oxide Vbd is compromised by germanium oxide formation at the L1 and high-k boundary. Thus, the strategy of FinFET junction optimization needs to consider not only transistor performance but also the gate oxide integrity.

Dual-curvature cavity for improved p-type FinFET performance

“…In planar CMOS technology, embeded-SiGe (eSiGe) benefits p-type transistor with higher hole mobility from channel strain and lower contact resistance from low semiconductormetal Schottky energy barrier [1]. As the leading edge technology migrates to FinFET, eSiGe continuous to serve as the source/drain (S/D) for p-type transistors [2][3][4][5]. In FinFET technology, the eSiGe S/D volume is critical for transistor performance because it modulates not only the strain over the channel, but also the contact area and thus the contact resistance [5].…”

“…Ball-shaped cavity is preferred in FinFET technology than sigma-shaped cavity [3][4][5] for it has better channel length uniformity from fin top to fin bottom. In this work, we study the FinFET cavity depth optimization and propose a new 'dual-curvature' cavity that improves the transistor performance on top of a well optimized ball-shaped cavity.…”

Performance boost using spacer-confined cavity for advanced FinFET technology

“…Over the past decade, the chip industry has been following Moore's law to scale down transistors with FinFET technology [1][2][3][4][5][6][7]. A distinguishing characteristic of FinFET technology is that the gate wraps around the fin.…”