Polymer coatings are applied to chips and passive components to provide stress relief between the device/component and the plastic package and/or to provide mechanical and environmental protection. The semiconductor industry is actively pursuing a one mask, photosensitive dielectric process for stressbuffer and secondary passivation of memory die. A one mask photo-benzocyclobutene (BCB) process is compared to traditional two mask wet etch processes. This new one mask process reveals 1/3 the total wafer processing time and equivalent reliability (traditional MIL 883C testing) for passivated 100 lead static random access memory components (SRAM's).
A series of back-side oxidation/front-side stacking-fault growth experiments have been carried out to determine the kinetic coefficients of self-interstitials in silicon. In these experiments, wet and dry oxidations of the back side of thinned silicon samples were used to inject self-interstitials from the back surfaces. The sample front surfaces were capped with oxide or nitride layers, and the concentration of self-interstitials at the capped surfaces were monitored by the growth or shrinkage of surface stacking faults. Experimental results have been analyzed using steady-state and transient models, based on the assumption that self-interstitials dominate the kinetic processes of intrinsic point defects. From these analyses, the relative recombination rates of self-interstitials at oxide and nitride boundary layers have been obtained, with an oxide layer found to absorb self-interstitials at about three times the rate of a nitride layer. The results also suggest that the surface recombination coefficients are time dependent rather than constant, as has been previously assumed.
Photosensitive Benzocyclobutene (Photo-BCB) has been widely reported on for use as a dielectric material in multilayer packaging applications, including: MCMs, IO redistribution, and flat panel display. Photo-BCB has many properties which are highly attractive for these applications, including: a simple processing scheme which is compatible with existing IC manufacturing techniques, low level of ionics, low moisture uptake, low cure temperatures, rapid thermal curing, high optical transparency, high planarization level, high thermal stability, high solvent resistance, very low outgassing, and a low dielectric constant.Photo-BCB is also being actively evaluated for wafer-level applications such as stress-buffer and passivation. In this paper, we will discuss the Photo-BCB properties and processing steps as they relate to these two applications. We will also compare the manufacturing scheme based on a one mask process for memory die, to the steps in a two mask process for stress-buffer and passivation.
We have investigated the effect of nickel and copper on defect formation in silicon employing the rapid thermal processing (RTP) scheme. Treatment by RTP induces haze in the silicon wafer front side when its back side is contaminated by either nickel or copper. Transmission electron microscopy studies showed that the haze consisted of metal silicide precipitates, which negates a previous suggestion that ‘‘oxidation-induced stacking faults’’ are the main defect forming the haze. The morphology and nature of these precipitates have been analyzed. The nickel silicide precipitates were found to be NiSi2 and the copper silicide precipitates are most likely CuSi (zinc blende structure). Both kinds of precipitates exhibited an epitaxial relationship with the silicon substrate and adopted the shape of an inverted pyramid or section of a pyramid. The present CuSi precipitate morphology differs totally from that obtained using furnace annealing, and is attributed to the availability of free-silicon surface as the main silicon self-interstitial sink. Implications for low-temperature ultralarge scale integration processing are discussed.
The retardaiion phenomenon of oxygen precipitation in Czochralski silicon has been studied simultaneously with the growth of surface stacking faults under a silicon nitride capping layer. The surface faults were intentionally introduced to monitor the bulk self-interstitial supersaturation in the crystal during precipitate growth. It was observed that an increase in the low-temperature nucleation anneal time resulted in a reduced rate of oxygen precipitation and an enhanced rate of surface stacking fault growth at high temperatures. This indicates that as the nucleation anneal time increases, silicon self-interstitials, which must be generated for precipitation to proceed, reach a high level of supersaturation and cause the annihilation of most nuclei generated during the nucleation anneal. 4215 J.
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