We describe the design and implementation of a bit-serial, four-bit, binary optical counter. The counter was designed and simulated using a digital optical simulation program developed for this purpose. It consists of five switches, a 4-bit fiber loop memory to store the count, four splitters, and fibers to interconnect the components. The counter is presently limited to a clock rate of 50 MHz because of the propagation delay in the single-bit time feedback loop. As designed, the same hardware may be used to count any even number of bits simply by changing the lengths of two fiber loops. The counter is unique in that it does not employ latches or other synchronizing memory elements, rather relying on a time-of-flight architecture. We describe the system issues involved in construction of the counter as well as the novel requirements on the switch drive electronics. We then outline the issues still to be addressed for the current counter and conclude with suggested design alternatives to improve its operation and increase its clock rate.
The design of a complete, stored-program digital optical computer is described. A fully functional, proof-of-principle prototype can be achieved by using LiNbO(3) directional couplers as logic elements and fiber-optic delay lines as memory elements. The key design issues are computation in a realm where propagation delays are much greater than logic delays and implementation of circuits without fip-flops. The techniques developed to address these issues yield architectures that do not change as their clocking speed is scaled upward and the size is scaled downward proportionally; these are called speed-scalable architectures. Signal amplitude restoration and resynchronization are accomplished by the novel technique of switching in a fresh copy of the system clock. Device characteristics that are important to the proof-of-principle demonstration are discussed, including the special properties and limitations that are important when designing with them. Design principles are exemplified by the design of an n-bit counter. Following this, the design for a stored-program bit-serial computer is described. We estimate that the described prototype architecture can be operated in the 100-MHz region with off-the-shelf components, and in the O. 1-1-THz region with foreseeable future components.
We have constructed what is to our knowledge the first speed-of-light 100-MHz digital optical counter using directional coupler switches and single-mode fibers. The counter has operated with both 4- and 6-bit counts, with the use of two different counter designs. In addition, we have demonstrated operation of two simultaneous and independent 4-bit counters running on the same hardware by time-division multiplexing the hardware. This approach allows effective clock rates many times the individual machine clock rate and is limited only by the switching speed. For large latency systems, this approach offers the promise of gigahertz clock rates for digital optical computers.
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