Summary
A new technique ON/OFf logIC (ONOFIC) is proposed in this paper for designing domino logic circuits in fin‐field effect transistor (FinFET) deep submicron technology. In this technique, a block named ONOFIC is inserted between pull‐up network (PUN) and pull‐down network (PDN) of domino circuits. The proposed technique is simulated in FinFET short gate (SG) and low power (LP) mode. The subthreshold current which plays a major role to determinate leakage power is very low in this technique. Two‐, 4‐, 8‐, and 16‐input OR gates are simulated with 32‐nm node FinFET technology. In FinFET LP mode, the subthreshold leakage power of the proposed technique is reduced by 15% to 24.3% at 25°C and reduced by 8.71% to 23.4% at 110°C compared with standard domino circuits. The subthreshold leakage power of the proposed circuit is reduced by 19.2% to 57.3% at 25°C and reduced by 17.6% to 60.7% at 110°C compared with leakage control transistor (LECTOR)‐based circuits. In FinFET SG mode, the subthreshold leakage power of the proposed technique is reduced by 7.69% to 17.7% at 25°C and reduced by 0 to 7.85% at 110°C compared with standard domino circuits. The subthreshold leakage power of the proposed circuit is reduced by 60.4% to 73.9% at 25°C and reduced by 45.1% to 65.5% at 110°C compared with LECTOR‐based circuits. The proposed technique is also efficient to reduce subthreshold leakage power in deep nanometer technology nodes from 7 to 20 nm.
The leakage current is prime concern in the modern portable battery operated device. However, various techniques are presented and performance is evaluated using MOSFET and FinFET devices. To further reduce leakage current for improved battery backup in portable devices, new devicesnamely Carbon Nano Tube Field Effect transistors (CNTFETs) can be used for design of different digital circuits. In this paper, subthreshold leakage power of dual chiral CNTFET based domino circuit is investigated and also the results are compared with single chiral CNTFET domino circuits. For better performance, threshold voltage of CNTFET in critical path is varied by changing the diameter or chirality of carbon nanotube. Subthreshold leakage power saving in dual chiral standard and LECTOR based domino circuits for OR2, OR4, OR8 & OR16 for low temperature (25°C) & low input ranges from 90.36-95.96% and from 91.97-97.3%; for low temperature & high input ranges from 90.66-95.23% and from 92.85-96.39%; for high temperature (110°C) & low input ranges from 89.24-99.73% and from 27.5-99.83%; for high temperature & high input ranges from 89.65-97.86% and from 91.85-99.76% when compared with single chiral standard and LECTOR based domino circuits respectively.
HighlightsThe major contributions of the paper are as follows:1. A comprehensive analysis on the state-of-the-art leakage reduction techniques.2. An analysis of the leakage reduction using CNTFET devices.3. An improved leakage reduction technique using dual chiral CNTFET in standard footerless and LECTOR based domino circuits.4. The simulation results show subthreshold leakage current reduction upto 97.3% at 25°C and 99.76% at 110°C.
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