ONOFIC Pull-Up Approach in Domino Logic Circuits Using FinFET for Subthreshold Leakage Reduction

Magraiya, Vijay Kumar; Gupta, Tarun Kumar

doi:10.1007/s00034-018-0980-8

Cited by 9 publications

(3 citation statements)

References 18 publications

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“…This method simulates multi-input OR gates using a 32-nm FinFET technology node and compares them to conventional footless domino gates. This technique reduces the subthreshold leakage and hence reduces leakage power dissipation [25,26].…”

Section: Previous Literaturementioning

confidence: 99%

INDIDO: A novel low-power approach for domino logic circuits

Mushtaq,

Akram,

Prasad

et al. 2024

Phys. Scr.

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Power dissipation in Nanoelectronic circuits at advanced technology nodes is dominated by leakage power dissipation. This is due to an increase in short channel effects in the scaled transistors. The VLSI industry is seeking alternative options to enhance the performance of portable electronic systems by ensuring higher speed and reduced power dissipation. In the ultra-deep submicron (DSM) regime, a new device called the fin-shaped field effect transistor (FinFET) was developed to replace CMOS technology. FinFET, a multi-gate device, significantly reduces power dissipation compared to planer MOS (Metal Oxide Semiconductor ) transistor, but it doesn't entirely resolve the issue. To further reduce power dissipation in the ultra DSM regime, low power approaches are required. Domino logic, a widely-used dynamic logic, is commonly utilized in high-speed VLSI architectures. In this research work, a novel INput Dependent Inverter DOmino (INDIDO) logic approach for low-power domino logic circuits using FinFET devices is proposed. A comparative analysis between the proposed INDIDO method and the existing approaches is performed for domino logic circuits for various performance metrics at the 16 nm technology node. In this research, various circuits like domino buffer, domino OR, domino AND, domino XOR and domino half adder are designed using the proposed INDIDO approach. The proposed INDIDO FinFET buffer circuit offers significant improvement in energy efficiency and FOM (Figure of Merit) by 53.18 % and 82% respectively as compared to conventional FinFET footed domino buffer circuit. Beside this, proposed circuits like INDIDO OR, INDIDO AND, INDIDO XOR and INDIDO Half adder circuit follow the same trend as INDIDO buffer circuit and show better performance parameters in comparison to the existing low power domino approaches as well. In addition to this, the proposed INDIDO buffer circuits are also analyzed for PVT(process voltage and temperature) variability. This whole analysis makes us to conclude that proposed INDIDO approach reduces power dissipation and delay penalty, have high noise tolerance capacity, more immunity against PVT variations and high energy efficiency in comparison to the already existing techniques.

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Section: Previous Literaturementioning

confidence: 99%

INDIDO: A novel low-power approach for domino logic circuits

Mushtaq,

Akram,

Prasad

et al. 2024

Phys. Scr.

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“…Moradi et al [11] designed high performance domino circuits including leakage and proposed several logic circuits using FinFET device which is useful for reducing total leakage power. Magraiya et al [12,13] also worked for reduction of subthreshold leakage power in FinFET domino circuits with the help of ONOFIC & ONOFIC pull-up approach and achieved subthreshold leakage reduction.…”

Section: Literature Reviewmentioning

confidence: 99%

Design of CNTFET based Domino Wide OR Gates using Dual Chirality for Reducing Subthreshold Leakage Current

Magraiya

Gupta

Garg³

2022

Silicon

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The leakage current is prime concern in the modern portable battery operated device. However, various techniques are presented and performance is evaluated using MOSFET and FinFET devices. To further reduce leakage current for improved battery backup in portable devices, new devicesnamely Carbon Nano Tube Field Effect transistors (CNTFETs) can be used for design of different digital circuits. In this paper, subthreshold leakage power of dual chiral CNTFET based domino circuit is investigated and also the results are compared with single chiral CNTFET domino circuits. For better performance, threshold voltage of CNTFET in critical path is varied by changing the diameter or chirality of carbon nanotube. Subthreshold leakage power saving in dual chiral standard and LECTOR based domino circuits for OR2, OR4, OR8 & OR16 for low temperature (25°C) & low input ranges from 90.36-95.96% and from 91.97-97.3%; for low temperature & high input ranges from 90.66-95.23% and from 92.85-96.39%; for high temperature (110°C) & low input ranges from 89.24-99.73% and from 27.5-99.83%; for high temperature & high input ranges from 89.65-97.86% and from 91.85-99.76% when compared with single chiral standard and LECTOR based domino circuits respectively. HighlightsThe major contributions of the paper are as follows:1. A comprehensive analysis on the state-of-the-art leakage reduction techniques.2. An analysis of the leakage reduction using CNTFET devices.3. An improved leakage reduction technique using dual chiral CNTFET in standard footerless and LECTOR based domino circuits.4. The simulation results show subthreshold leakage current reduction upto 97.3% at 25°C and 99.76% at 110°C.

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“…Moradi et al [11] designed high performance domino circuits including leakage and proposed several logic circuits using FinFET device which is useful for reducing total leakage power. Magraiya et al [12,13] It is observed from the above research work that the existing leakage reduction techniques with CMOS & FinFET devices are still not minimizing the leakage current e ciently. Further there is very less analysis on the leakage current of circuits with CNTFETs.…”

Section: Literature Reviewmentioning

confidence: 99%

Design of CNTFET Based Domino Wide OR Gates Using Dual Chirality for Reducing Subthreshold Leakage Current

Magraiya¹,

Gupta²,

Garg³

2021

Preprint

Self Cite

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The leakage current is prime concern in the modern portable battery operated device. However, various techniques are presented and performance is evaluated using MOSFET and FinFET devices. To further reduce leakage current for improved battery backup in portable devices, new devicesnamely Carbon Nano Tube Field Effect transistors (CNTFETs) can be used for design of different digital circuits. In this paper, subthreshold leakage power of dual chiral CNTFET based domino circuit is investigated and also the results are compared with single chiral CNTFET domino circuits. For better performance, threshold voltage of CNTFET in critical path is varied by changing the diameter or chirality of carbon nanotube. Subthreshold leakage power saving in dual chiral standard and LECTOR based domino circuits for OR2, OR4, OR8 & OR16 for low temperature (25°C) & low input ranges from 90.36- 95.96% and from 91.97-97.3%; for low temperature & high input ranges from 90.66-95.23% and from 92.85-96.39%; for high temperature (110°C) & low input ranges from 89.24- 99.73% and from 27.5-99.83%; for high temperature & high input ranges from 89.65-97.86% and from 91.85-99.76% when compared with single chiral standard and LECTOR based domino circuits respectively.

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ONOFIC Pull-Up Approach in Domino Logic Circuits Using FinFET for Subthreshold Leakage Reduction

Cited by 9 publications

References 18 publications

INDIDO: A novel low-power approach for domino logic circuits

INDIDO: A novel low-power approach for domino logic circuits

Design of CNTFET based Domino Wide OR Gates using Dual Chirality for Reducing Subthreshold Leakage Current

Design of CNTFET Based Domino Wide OR Gates Using Dual Chirality for Reducing Subthreshold Leakage Current

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