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manufacturable, high throughput process. Currently, In this paper, we present the latest advancements 75 mm diameter InP substrates are used and EBL of sub 50 nm InGaAs/InAlAs/InP High Electron lithography requires less than 1 hour for exposure Mobility Transistor (InP HEMT) devices that have over the wafer. A maximum wafer throughput of 150 achieved extrapolated Fmax above 1 THz. This wafers per week and 100 wafers per week on 100 mm extrapolation is both based on unilateral gain (1.2 diameter wafers would be possible on a single EBL THz) and maximum stable gain/maximum available system. A 2nd key enhancement is the reduction of gain (1.1 THz) extrapolations, with an associated fT of ohmic contact resistance through a higher doped cap 385 GHz. This extrapolation is validated by the layer design coupled with a InAs/InGaAs channel demonstration of a 3-stage common source low noise grown by molecular beam epitaxy. The sheet MMIC amplifier which exhibits greater than 18 dB gain resistance of the epitaxial layers is lowered to 75 at 300 GHz and 15 dB gain at 340 GHz. ohm/sq. (compared to 110 ohm/sq. in the baseline InP HEMT profile) and the mobility was improved to as INTRODUCTION high as 15,000 cmA2N-sec (compared to 12,000 Future systems will extend the need for higher cmA2/V-sec in the baseline InP HEMT profile). A low frequency and bandwidth devices and circuits beyond contact resistance of 0.05 ohm-mm and a high peak current capability and concepts. Rapid development transconductance as high as 2300 mS/mm was and advancement of solid state transistor and MMIC measured at 1V drain bias with a device breakdown technology has pushed extremely high cutoff typically of 2.5V and a maximum drain source voltage frequency and high maximum oscillation frequencies of 2V and good device pinchoff characteristics. (Fmax) in various technologies [1][2][3]. This paper describes the latest advancements of sub 50 nm InP HEMT DEVICE MEASUREMENTS InGaAs/InAlAs/InP High Electron Mobility Transistor S-parameter measurements on extended (InP HEMT) devices that have achieved extrapolated reference plane 2 finger 20 um grounded CPW Fmax above 1 THz for the first time to the best of our devices with 2-mil thick substrates were measured knowledge and is validated by the demonstration of a from 1-110 GHz. The grounded CPW and extended 3-stage low noise MMIC amplifier at 340 GHz with reference plane serve to reduce measurement and greater than 15 dB gain. calibration issues such as probe coupling and substrate modes. The device performance is deInP HEMT DEVICE FABRICATION embedded using an EM simulated SOLT calibration To develop the THz Fmax InP HEMT device, structures fabricated on-wafer. H21 and maximum several process enhancements were implemented on stable gain (MSG) are relatively smooth and follows NGST's baseline InP HEMTs [4]. One key process the theoretical slope of -20 dB/decade and -10 enhancement was the reduction of gate length from dB/decade slope closely from 1 -110 GHz. The 70 to less than 50 nm. Based on cross sections ext...

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In this paper, the integrated-antenna concept is applied to push-pull power amplifiers (PA's). In this approach, the antenna serves as an out-of-phase power combiner and tuned load for higher harmonics. This new architecture effectively has a near-zero loss output hybrid, and results in a high-efficiency PA. The first example is a narrow-band push-pull amplifier integrated with a dual-feed patch antenna. At an operating frequency of 2.5 GHz, a maximum measured power-added efficiency (PAE) of 55% is achieved. The second example is a broadband push-pull amplifier integrated with a dual-feed slot antenna amplifier operating at 2.46 GHz has a peak PAE of 63%, and PAE is better than 55% in an 8% bandwidth. Additionally, 48% PAE is achieved with code-division multiple-access modulation and adjacent-channel power ratio better than 042 dBc at a 1.25-MHz offset.