Defect detection and classification in semiconductor wafers has received an increasing attention from both industry and academia alike. Wafer defects are a serious problem that could cause massive losses to the companies' yield. The defects occur as a result of a lengthy and complex fabrication process involving hundreds of stages, and they can create unique patterns. If these patterns were to be identified and classified correctly, then the root of the fabrication problem can be recognized and eventually resolved. Machine learning (ML) techniques have been widely accepted and are well suited for such classification-/identification problems. However, none of the existing ML model's performance exceeds 96% in identification accuracy for such tasks. In this paper, we develop a state-of-the-art classifying algorithm using multiple ML techniques, relying on a general-regression-network-based consensus learning model along with a powerful randomization technique. We compare our proposed method with the widely used ML models in terms of model accuracy, stability, and time complexity. Our method has proved to be more accurate and stable as compared to any of the existing algorithms reported in the literature, achieving its accuracy of 99.8%, stability of 1.128, and TBM of 15.8 s.
The grain growth which occurs during the self-annealing in copper electrodeposits was investigated by in situ observation with an electron backscattered diffraction technique. From these observations, it was found that a newly created twin was initiated on the front interface of growing twin and that the transverse direction for the growth was ͗110͘. Most of the twins had the ⌺3 twin boundary of ͕111͖͗110͘. The formation of the twin and its peculiar growth direction could be explained quite well based on the hypothesis that the growth front interface is one of the ͕111͖ planes.
The effects of grain size and pattern geometry on the etching rate were investigated by using our invented pattern, and each pattern has a same height of electrodeposits regardless of pattern size after electroplating. It was found out that the logarithmic value of the etching rate is inversely linear with the pattern width at self-annealed specimen. In other words, as the pattern width decreases, the etching rate increases exponentially. Such tendency of the etching rate is owing to the result that the interfacial energies of pattern surface and grain boundary per unit volume increase by the decrease of pattern width. In contrast, the as-deposited sample shows a flat etching rate for pattern sizes. In addition, at the narrow patterns with a pattern width of below 220 nm, the etching rate in the nanocrystalline structure of the as-deposited sample is lower than in the grain grown structure of the self-annealed sample. It can be surmised that the stresses caused by interfacial energies may be relaxed by the nanocrystalline structure in the as-deposited sample.
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