Process Variation has become a crucial challenge on both interconnect delay and reliability of nanometer integrated circuit designs. Furthermore, the dramatic increase of power consumption and integration density has led to high operating temperature. Temperature, as well as electromigration (EM) and power, also significantly affects the delay and reliability of interconnects. Considering process variation, we present the first work to use statistical methods to optimize the circuit area under timing, thermal and power constraints by gate and interconnect sizing optimization. We model the problem as a second-order conic program and solve it with the interior-point method. Experimental results show that our statistical algorithm can find desired solutions that satisfy all delay, power, and thermal constraints. Our statistical algorithm on average improves the circuit areas by respective 51.12%, 39.21%, and 25.60% with 70%, 84.1%, and 99.9% yields after wire and gate sizing.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.