Statistical circuit optimization considering device andinterconnect process variations

Lin, I-Jye; Ling, Tsui-Yee; Chang, Yao-Wen

doi:10.1145/1231956.1231966

Cited by 4 publications

(3 citation statements)

References 23 publications

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“…5 shows the accuracy of our simplified POF o i . In general, the SOCP is known to have O(N 1.3 ) complexity [34], [35], where N is the number of variables and requires at most 30 iterations to solve even large problems [24]. Thus, it should be adequate to handle a VLSI track routing problem.…”

Section: A Motivation and Strategymentioning

confidence: 99%

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Track Routing and Optimization for Yield

Cho

Xiang

Puri

et al. 2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we propose track routing and optimization for yield (TROY), the first track router for the optimization of yield loss due to random defects. As the probability of failure (POF), which is an integral of the critical area and the defect size distribution, strongly depends on wire ordering, sizing, and spacing, track routing can play a key role in effective wire planning for yield optimization. However, a straightforward formulation of yield-driven track routing can be shown to be integer nonlinear programming, which is a nondeterministic polynomial-time complete problem. TROY overcomes the computational complexity by combining two effective techniques, i.e., the minimum Hamiltonian path (MHP) from graph theory and the second-order cone programming (SOCP) from mathematical optimization. First, TROY performs wire ordering to minimize the critical area for short defects by finding an MHP. Then, TROY carries out optimal wire sizing/spacing through SOCP optimization based on the given wire order. Since the SOCP can be optimally solved in near linear time, TROY efficiently achieves globally optimal wire sizing/spacing for the minimal POF.Index Terms-Minimum Hamiltonian path (MHP), physical design, random defects, second-order cone programming (SOCP), track routing, yield.

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Section: A Motivation and Strategymentioning

confidence: 99%

“…Then, the formulation in Fig. 9 can be solved optimally and efficiently by the primal-dual interior-point method with O(N 1.3 ) bound, where N is the number of variables [34], [35]; thus, the solution will provide the optimal wire sizing and spacing for maximum yield. Fig.…”

Section: Globally Optimal Wire Sizing and Spacingmentioning

confidence: 99%

Track Routing and Optimization for Yield

Cho

Xiang

Puri

et al. 2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The shift to probabilistic design methodologies has produced a number of gate-level variation-aware optimization techniques [1] [2]. While progress at the gate-level is encouraging, the large productivity gains available in high-level synthesis (HLS) make it attractive and necessary to address the issue of process variations at a higher level of abstraction.…”

Section: Introductionmentioning

confidence: 99%

FastYield: Variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization

Lucas¹,

Cromar²,

Chen³

2009

2009 Asia and South Pacific Design Automation Conference

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-While technology scaling has presented many new and exciting opportunities, new design challenges have arisen due to increased density, and delay and power variations. Highlevel synthesis has been touted as a solution to these problems, as it can significantly reduce the number of man hours required for a design by raising the level of abstraction. In this paper, we propose a new variation-aware high-level synthesis binding/module selection algorithm, named FastYield, which takes into consideration multiplexers, functional units, registers, and interconnects. Additionally, FastYield connects with the lower levels of the design hierarchy through its inclusion of a timing driven floorplanner guided by a statistical static timing analysis (SSTA) engine which is used to modify/enhance the synthesis solution. FastYield is able to incorporate spatial correlations of process variations in its optimization, which are shown to affect performance yield. On average, FastYield achieves a clock period that is 14.5% smaller, and a performance yield gain of 78.9%, when compared to a variation-unaware algorithm. By making use of accurate timing information, FastYield's rebinding improves performance yield by an average of 9.8% over the initial binding, for the same clock period. To the best of our knowledge, this is the first high-level synthesis binding/module selection algorithm that is layout-driven and variation aware.

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An efficient algorithm for statistical circuit optimization using lagrangian relaxation

Lin

Chang

2007

2007 IEEE/ACM International Conference on Computer-Aided Design

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Statistical circuit optimization considering device andinterconnect process variations

Cited by 4 publications

References 23 publications

Track Routing and Optimization for Yield

Track Routing and Optimization for Yield

FastYield: Variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization

An efficient algorithm for statistical circuit optimization using lagrangian relaxation

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