Parallel counters are the building blocks of partial product reduction tree (PPRT) circuits, which are required for high-performance multiplication. In this paper we will implement novel counters using a hybrid of domino and threshold logic. A test 64 × 64 PPRT using these counters was found to reduce latency by 39% and device count by 38% compared to the domino logic equivalent.
Parallel multipliers are of increasing importance for VLSI design, largely driven by the significant increase in demand for computer graphics and digital signal processing. The fastest (and, when pipelined, most areaefficient) multiplier class is partial product reduction tree (PPRT) based multipliers. The previous best known heuristic for PPRT design (published by Stelling et al. 1 ) is capable of producing the fastest possible circuits but suffers an infeasible computational burden. This paper introduces some results which significantly reduce the search space of this heuristic. Consequently, the speed of netlist generation is increased, and the circuits generated retain optimal performance. In addition, larger optimal multipliers may be synthesised due to the easing of the computational burden.
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