Abstract:Parallel multipliers are of increasing importance for VLSI design, largely driven by the significant increase in demand for computer graphics and digital signal processing. The fastest (and, when pipelined, most areaefficient) multiplier class is partial product reduction tree (PPRT) based multipliers. The previous best known heuristic for PPRT design (published by Stelling et al. 1 ) is capable of producing the fastest possible circuits but suffers an infeasible computational burden. This paper introduces som… Show more
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