This paper describes the design and implementation of an SRAM-Programmable Field-Configurable Memory (FCM), which has the flexibility to form over two hundred different memory configurations, each with up to four individual memories. The prototype Field-Configurable Memory has four 1Kb memory blocks, each of which can be configured into four different aspect ratios. It requires just 40 configuration bits and is only 38% larger and 46% slower than the ASIC memory upon which it is based. User memories implemented on this chip require from 16 to 23 times less area than if they were implemented on a Xilinx 4000 series memory architecture. Although this is a standalone FCM implementation, the design can be embedded as part of an FPGA.
As programmable logic grows more viable for implementing full design systems, performance has become a primary issue for programmable logic device architectures. This paper presents the high-level design of Dali, a PLD architecture specifically aimed at performancedriven applications. We will present significant portions of the background research that contributed to our architectural decisions, an overview of the core routing architecture and benchmarking experiments used to evaluate the prototype device.
As programmable logic grows more viable for implementing full design systems, performance has become a primary issue for programmable logic device architectures. This paper presents the high-level design of Dali, a PLD architecture specifically aimed at performancedriven applications. We will present significant portions of the background research that contributed to our architectural decisions, an overview of the core routing architecture and benchmarking experiments used to evaluate the prototype device.
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