We present a theoretical study of electron mobility in cylindrical gated silicon nanowires at 300 K based on the Kubo-Greenwood formula and the self-consistent solution of the Schrödinger and Poisson equations. A rigorous surface roughness scattering model is derived, which takes into account the roughness-induced fluctuation of the subband wave function, of the electron charge, and of the interface polarization charge. Dielectric screening of the scattering potential is modeled within the random phase approximation, wherein a generalized dielectric function for a multi-subband quasi-one-dimensional electron gas system is derived accounting for the presence of the gate electrode and the mismatch of the dielectric constant between the semiconductor and gate insulator. A nonparabolic correction method is also presented, which is applied to the calculation of the density of states, the matrix element of the scattering potential, and the generalized Lindhard function. The Coulomb scattering due to the fixed interface charge and the intra- and intervalley phonon scattering are included in the mobility calculation in addition to the surface roughness scattering. Using these models, we study the low-field electron mobility and its dependence on the silicon body diameter, effective field, dielectric constant, and gate insulator thickness.
In our attempts to scale FETs to the 10 nm length, alternatives to conventional Si CMOS are sought on the grounds that: (1) Si seems to have reached its technological and performance limits and (2) the use of alternative highmobility channel materials will provide the missing performance. With the help of numerical simulations here we establish the reasons why indeed Si seems to have hit an intrinsic performance barrier and whether or not high mobility semiconductors can indeed grant us our wishes. The role of long-and short-range electron-electron interactions are revisited together with a recent analysis of the historical performance trends. The density-of-states (DOS) bottleneck and source starvation issues are also reviewed to see what advantage alternative substrates may bring us. Finally, the well-known 'virtual source model' is analyzed to assess whether it can be used as a quantitative tool to guide us to the 10 nm gate length.
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