In recent years the power consumption of highperformance computing clusters has become a growing problem because the number and size of cluster installations has been rising. The high power consumption of clusters is a consequence of their design goal: High performance. With low utilization, cluster hardware consumes nearly as much energy as when it is fully utilized. Theoretically, in these low utilization phases cluster hardware can be turned off or switched to a lower power consuming state.We designed a model to estimate power consumption of hardware based on the utilization. Applications are instrumented to create utilization trace files for a simulator realizing this model. Different hardware components can be simulated using multiple estimation strategies. An optimal strategy determines an upper bound of energy savings for existing hardware without affecting the time-to-solution. Additionally, the simulator can estimate the power consumption of efficient hardware which is energy-proportional. This way the minimum power consumption can be determined for a given application. Naturally, this minimal power consumption provides an upper bound for any power saving strategy.After evaluating the correctness of the simulator several different strategies and energy-proportional hardware are compared.T. Minartz ( ) · T. Ludwig

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Energy consumption has become a major topic in high performance computing in the last years. We present an approach to efficiently manage the power states of an poweraware cluster, including the processor, the network cards and the disks.To profit from the lower power consumption of these states we followed the approach to transfer application knowledge (e.g. future hardware use) to a daemon which efficiently manages the hardware device states per cluster node. After introducing our measurement environment we evaluated the general power saving potential of our AMD and Intel computing nodes. Two example high performance applications are showcases for an initial instrumentation which results in a reduction of the Energy-to-Solution between 4 and 8 % with slight increases of the Time-to-Solution.

Energy consumption is one of the major topics in high performance computing (HPC) in the last years. However, little effort is put into energy analysis by developers of HPC applications. We present our approach of combined performance and energy analysis using the performance analysis tool-set Scalasca. Scalascas parallel wait-state analysis is extended by a calculation of the energy-saving potential if a lower power-state can be used.

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