The focus of this study is on the role of Cu content in the dissolution kinetics of Cu in high-Sn solders during the solid/liquid reaction accompanied by interfacial intermetallic compound formation. Small additions of Cu (0.7%, 1.5%) in high-Sn solders dramatically decrease the dissolution rate of Cu at low temperatures. Sn-3.5Ag, as expected, has a dissolution rate similar to that of pure Sn. The difference in dissolution rate of Cu in various molten solders is explained in terms of the solubility limit of Cu in molten solders based on the Cu-Sn phase diagram. The correlation between the metallurgical aspects of interfacial eta(Cu6Sn5) phase formation and dissolution kinetics of Cu in molten solders leads to an understanding of the mechanism that controls the dissolution rate of Cu in molten solders
As solder joints become increasingly miniaturized to meet the severe demands of future electronic packaging, it is vitally important to consider whether the solder joint size and geometry could become reliability issues and thereby affect implementation of the Pb-free solders. In this study, three bumping techniques, i.e., solder dipping, stencil printing followed by solder reflow, and electroplating of solders with subsequent reflow, were used to investigate the interfacial interactions of molten Sn-3.5Ag, Sn-3.8Ag-0.7Cu, and pure Sn solders on a copper pad at 240 degrees C. The resultant interfacial microstructures, coming from a variety of Cu pads, with sizes ranging from I mm to 25 mu m, and representing different solder bump geometries, have been investigated. In addition, a two-dimensional thermodynamic/kinetic model has been developed to assist the understanding of the kinetics of interdiffusion and the formation of interfacial intermetallic compounds. Experimental results and theoretical predictions both suggest that the solder bump size and geometry can influence the as-soldered microstructure; therefore, this factor should be taken into consideration for the design of future reliable ultrafine Pb-free solder joints
Purpose-In the past 15 years stretchable electronic circuits have emerged as a new technology in the domain of assembly, interconnections and sensor circuits and assembly technologies. In the meantime a wide variety of processes with the use of many different materials have been explored in this new field. The purpose of the current contribution is for the authors to present an approach for stretchable circuits which is inspired by conventional rigid and flexible printed circuit board (PCB) technology. Two variants of this technology are presented: stretchable circuit board (SCB) and stretchable mould interconnect (SMI). Design/methodology/approach-Similarly as in PCB 17 or 35 mm thick sheets of electrodeposited or rolled-annealed Cu are structured to form the conductive tracks, and off-the-shelf, standard packaged, rigid components are assembled on the Cu contact pads using lead-free solder materials and reflow processes. Stretchability is obtained by shaping the Cu tracks not as straight lines, like in normal PCB design, but as horseshoe shaped meanders. Instead of rigid or flexible board materials, elastic materials, predominantly PDMS (polydimethylsiloxane), are used to embed the conductors and the components, thus serving as circuit carrier. The authors include some mechanical modeling and design considerations, aimed at the optimization of the build-up and combination of elastic, flexible and rigid materials towards minimal stress and maximum mechanical reliability in the structures. Furthermore, details on the two production processes are given, reliability findings are summarised, and a number of functional demonstrators, realized with the technologies, are described. Findings-Key conclusions of the work are that: supporting the metal meanders with a flexible carrier prior to embedding in an elastic substrate substantially increases the reliability under mechanical stress (cyclic uniaxial stretching) of the stretchable interconnect and the transition areas between rigid components and stretchable interconnects are the zones which are most sensitive to failure under mechanical stress. Careful design and technology implementation is necessary, providing a gradual transition from rigid to flexible to stretchable parts of the circuit. Originality/value-Technologies for stretchable circuits, with the same level of similarity to standard PCB manufacturing and assembly, and thus with the same high potential for transfer to an industrial environment and for mass production, have not been shown before.
Purpose - The purpose of this paper is to present results from the EC funded project SHIFT (Smart High Integration Flex Technologies) on the embedding in and the assembly on flex substrates of ultrathin chips. Design/methodology/approach - Methods to embed chips in flex include flip-chip assembly and subsequent lamination, or the construction of a separate ultra-thin chip package (UTCP) using spin-on polyimides and thin-film metallisation technology. Thinning and separation of the chips is done using a "dicing-by-thinning" method. Findings - The feasibility of both chip embedding methods has been demonstrated, as well as that of the chip thinning method. Lamination of four layers of flex with ultrathin chips could be achieved without chip breakage. The UTCP technology results in a 60 mu m package where also the 20 mu m thick chip is bendable. Research limitations/implications - Further development work includes reliability testing, embedding of the UTCP in conventional flex, and construction of functional demonstrators using the developed technologies. Originality/value - Thinning down silicon chips to thicknesses of 25 mu m and lower is an innovative technology, as well as assembly and embedding of these chips in flexible substrates
A comparative study of solid/solid interfacial reactions of electroless Ni-P (15at.%P) with lead-free solders, Sn-0.7Cu, Sn-3.5Ag, Sn-3.8Ag-0.7Cu and pure Sn,, was carried out by performing thermal aging at 150oC up to 1000 h. For pure Sn and Sn-3.5Ag solder, three distinctive layers, Ni3Sn4, SnNiP and Ni3P, were observed in between the solder and electroless Ni-P; while for Sn-0.7Cu and Sn-3.8Ag-0.7Cu solders, two distinctive layers, (CuNi)6Sn5 and Ni3P, were observed. The differences in morphology and growth kinetics of the intermetallic compounds (IMCs) at the interfaces between electroless Ni-P and lead-free solders were investigated, as well as the growth kinetics of the P-enriched layers underneath the interfacial IMC layers. With increasing aging time, the coarsening of interfacial Ni3Sn4 IMC grains for pure Sn and Sn-3.5Ag solder was significantly greater than that of the interfacial (CuNi)6Sn5 IMC grains for Sn-0.7Cu and Sn-3.8Ag-0.7Cu solders. Furthermore, the Ni content in interfacial (CuNi)6Sn5 phase slightly increased during aging. A small addition of Cu (0.7 wt.%) resulted in differences in the type, morphology and growth kinetics of interfacial IMCs. By comparing the metallurgical aspects and growth kinetics of the interfacial IMCs and the underneath P-enriched layers, the role of initial Cu and Ag in lead-free solders is better understood
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