This article presents a strategy to model the dynamics performed by vehicles in a freeway. The proposal consists on encode the movement as a set of finite states. A watershed-based segmentation is used to localize regions with highprobability of motion. Each state represents a proportion of a camera projection in a two-dimensional space, where each state is associated to a symbol, such that any combination of symbols is expressed as a language. Starting from a sequence of symbols through a linear algorithm a free-context grammar is inferred. This grammar represents a hierarchical view of common sequences observed into the scene. Most probable grammar rules express common rules associated to normal movement behavior. Less probable rules express themselves a way to quantify non-common behaviors and they might need more attention. Finally, all sequences of symbols that does not match with the grammar rules, may express itself uncommon behaviors (abnormal). The grammar inference is built with several sequences of images taken from a freeway. Testing process uses the sequence of symbols emitted by the scenario, matching the grammar rules with common freeway behaviors. The process of detect abnormal/normal behaviors is managed as the task of verify if any word generated by the scenario is recognized by the grammar.
This paper presents an algorithm with low computational complexity for classifying and recognizing characters based on a random sampling and high-dimensional binary spaces for the development of real-time applications. Character classification is performed using uniform random sampling as the feature selection process, subsequently performing encoding as binary strings.Associative memories are commonly used as general classifiers with linear criteria to discriminate between data points. In most classifiers, the ability to efficiently detect class membership depends entirely on the expressiveness of the attributes used to encode the data. Each binary pattern encodes the distinct characteristics of several glyphs. Character features are represented as elements of a high-dimensional binary space, where a criterion of the cluster is defined under the L 1 metric. The reduction in computational complexity is analyzed. The reduction in the number of character features through random sampling techniques makes it feasible to manage all the character information in physical architectures; therefore, this approach might use resources on a hardware platform with integer operators typically implemented at the hardware-register level. Finally, this approach is implemented in a parallel architecture Field-Programmable Gate Array (FPGA) and tested using a Database (DB) of different fonts, including distortions, therein showing that the efficiency is comparable to the other well-known approaches. KEYWORDS associative memory, Lernmatrix, OCR, real time, SteinbuchRecently, character recognition systems have become an essential field of research because of diverse applications, including handwritten character recognition 1,2 for license plate recognition, 3 address and zip code recognition, 4 and handwritten recognition. A typical character recognition system consists of the following components: image acquisition, segmentation, feature extraction, and classification. Various methods have been proposed for recognizing characters, such as Int J Circ Theor Appl. 2018;46: 1723-1732.wileyonlinelibrary.com/journal/cta
SummaryThis paper presents the development and implementation of an independent component analysis (ICA)–based background subtraction method on a field programmable gate array (FPGA) system on a chip (SoC) with embedded processor. The use of the classic form of ICA for this purpose results in a complex implementation with high hardware resource usage for an embedded system. Therefore, an alternative version of FastICA was developed that adapts directly to the parallelism offered by the FPGA. In addition, the incorporation of this version of ICA into the motion‐detection method exploits the architecture of the FPGA‐SoC with embedded processor. This recent technology complements the parallelism of the FPGA with the general‐purpose computing capacity of the processors while maintaining low energy consumption and a compact size. The above features are appropriate for autonomous devices that handle mainly background subtraction, while a central device receives this information and performs the remaining tasks required for the application. The use of processors allows a faster implementation and integration of the device into other systems in a simple manner, while the parallelism of the FPGA increases the processing speed by accelerating intensive numeric calculations. The results obtained from the implementation that uses both FPGA and the embedded processor of the SoC show an increase of 3300% in the number of frames per second compared with an implementation that uses only the embedded processor.
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