ICA-based background subtraction method for an FPGA-SoC

Carrizosa-Corral, Fernando; Váazquez-Cervantes, Alberto; Montes, Josué-Rafael; Hernández-Díaz, Teresa; Barriga-Rodríguez, Leonardo; Soto-Cajiga, Jorge Alberto; Hernandez, H.

doi:10.2352/issn.2470-1173.2017.13.ipas-203

Cited by 2 publications

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“…The Jacobi rotation differs from the identity matrix only at ℎ & ℎ rows and columns. For i th iteration, the pair (p, q) is selected according to the sequence of ( 16) or (17), which have a one-to-one correspondence. The completion of these n(n-1)/2 rotations is called a sweep, and denotes the total number of the two-sided Jacobi rotations in one sweep.…”

Section: B Evd By the Exact Jacobi Methodsmentioning

confidence: 99%

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An Efficient VLSI Architecture for FastICA by Using the Algebraic Jacobi Method for EVD

et al. 2021

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Blind source separation (BSS) is a problem that appears in many research fields. Fast Independent components analysis (FastICA) is one of the techniques to solve the problem. The researchers have verified the effectiveness of the technique through the offline analysis of the public datasets. The development of a real-time portable system involving such a computationally complex analysis requires an efficient hardware implementation of FastICA. A Field programmable gate array (FPGA) and an applicationspecific integrated circuit (ASIC) are two promising hardware platforms to implement FastICA. This work proposes a new method, called ALgebraic Jacobi Method (ALJM), for performing eigenvalue decomposition (EVD) required for the implementation of FastICA. We use a simplification, a polynomial approximation, and the Newton-Raphson method for calculating the Jacobi rotation. In this way, we ensure hardware reusability between the EVD stage and the weight vector estimation (WVE) stage of FastICA which reduces the computational complexity and the power consumption, without compromising its computation speed. We evaluate the ALJM-based FastICA by performing BSS on the linear mixtures of the deterministic and the random signals and comparing the performance results with the existing methods. After verifying its functionality and numerical stability, we propose a scalable systolic processing array (SPA) for the ALJMbased FastICA and implement it on Spartan-6 FPGA. By comparing the existing implementations of FastICA, in terms of speed, area, and power, we conclude that the ALJM-based FastICA is one of the most efficient methods for prototyping and commercializing a real-time portable system comprising FastICA.

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Section: B Evd By the Exact Jacobi Methodsmentioning

confidence: 99%

“…A System-on-Chip (SoC) based implementation of FastICA for dynamic background subtraction in real-time and portable vision devices is deployed in [17]. A field-programmable gate array (FPGA) based implementation of ICA is adopted in [18] for digital pre-distortion (DPD) in wireless communication systems.…”

Section: Introductionmentioning

confidence: 99%

An Efficient VLSI Architecture for FastICA by Using the Algebraic Jacobi Method for EVD

et al. 2021

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“…The background subtraction method developed and partially presented in Carrizosa-Corral et al 32 consists of three main blocks: background modeling, foreground extraction, and motion detection (see Figure 3). This section begins by providing an overview of a methodology for adapting algorithms on the FPGA-SoC, which was developed based on our analysis of the characteristics of FPGAs and processors and was used to conduct this study.…”

Section: Development and Implementation Of Ica-based Background Subtrmentioning

confidence: 99%

FPGA‐SoC implementation of an ICA‐based background subtraction method

Carrizosa-Corral

Vázquez-Cervantes

Montes

et al. 2018

Circuit Theory & Apps

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SummaryThis paper presents the development and implementation of an independent component analysis (ICA)–based background subtraction method on a field programmable gate array (FPGA) system on a chip (SoC) with embedded processor. The use of the classic form of ICA for this purpose results in a complex implementation with high hardware resource usage for an embedded system. Therefore, an alternative version of FastICA was developed that adapts directly to the parallelism offered by the FPGA. In addition, the incorporation of this version of ICA into the motion‐detection method exploits the architecture of the FPGA‐SoC with embedded processor. This recent technology complements the parallelism of the FPGA with the general‐purpose computing capacity of the processors while maintaining low energy consumption and a compact size. The above features are appropriate for autonomous devices that handle mainly background subtraction, while a central device receives this information and performs the remaining tasks required for the application. The use of processors allows a faster implementation and integration of the device into other systems in a simple manner, while the parallelism of the FPGA increases the processing speed by accelerating intensive numeric calculations. The results obtained from the implementation that uses both FPGA and the embedded processor of the SoC show an increase of 3300% in the number of frames per second compared with an implementation that uses only the embedded processor.

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ICA-based background subtraction method for an FPGA-SoC

Cited by 2 publications

References 0 publications

An Efficient VLSI Architecture for FastICA by Using the Algebraic Jacobi Method for EVD

An Efficient VLSI Architecture for FastICA by Using the Algebraic Jacobi Method for EVD

FPGA‐SoC implementation of an ICA‐based background subtraction method

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