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Nanotopography is the nanometer-scale height variation that occurs over lateral millimeter length scales on unpatterned silicon wafers [1][2]. This height variation can result in excess thinning of surface films during chemical mechanical polishing (CMP) of shallow trench isolation (STI) structures. The development of an accurate nanotopography CMP modeling and characterization procedure will allow for the proper diagnosis of potential problems due to wafer nanotopography in a given STI CMP process. In this work, a nanotopography modeling methodology is proposed which relates the length scale of nanotopography features to the length scale of the CMP process. A combined densityhtep-height polishing model indicates that when the nanotopography features occur over a range comparable to or shorter than the planarization length, appreciable thinning is predicted. A contact wear CMP model similarly shows that as the pad stiffness increases, film thinning also increases. These simulation results indicate that the effect of nanotopography on STI CMP may be a substantial concern.

this paper, we introduce a mathematical model for chemical mechanical polishing #CMP# of reverse tone etchback shallow trench isolation #STI# structures. We present a detailed formulation of the model and describe CMP experiments using a newly designed STI CMP characterization mask to validate the model. A methodology for extracting the model parameters is also proposed. An improved modeling methodology that incorporates density averaging effects fits the experimental data more accurately. Finally, we use the model to predict the effects of pre-CMP step height, pattern density, polish time, pad hardness, and slurry selectivity on dishing and nitride erosion. 2001 The Electrochemical Society. #DOI: 10.1149/1.1348266# All rights reserved. Manuscript submitted June 1, 2000; revised manuscript received November 21, 2000. Shallow trench isolation #STI#<F1

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A new set of wafer-scale patterns has been designed for analysis and modeling of key CMP effects. In particular, the goal of this work is to develop methods to characterize the planarization capability of a CMP process using simple measurements on wafer scale patterns. We examine means to pattern large trenches (e.g. 1 to 15 mm wide and 15 mm tall) or circles across 4” and 8” wafers, and present oxide polish results using both stacked and solo pads in conventional polish processes. We find that large separation (15 mm) between trenches enables cleaner measurement and analysis. Examination of oxide removal in the center of the trench as a function of trench width shows a saturation at a length comparable to the planarization length extracted from earlier studies of small-scale oxide patterns. Increase in polish pressure is observed to decrease this saturation point. Such wafer scale patterns may provide information on pad flexing limits in addition to planarization length, and promise to be useful in both patterned wafer CMP modeling and studies of wafer scale CMP dependencies such as nanotopography.

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