The objective of the presented work is to have a complete system level Orthogonal Frequency Division Multiplexing development platform where students both undergraduate and graduate can use it to explore and identify the different processing blocks available on modern communications systems. The platform will allow monitoring the inputs and outputs of every block to observe the signals as well as to be able to substitute each block by their own implementation. This could be done using a high level language such as Matlab/Simulink and C/C++, or the block can be substituted by a Hardware Description Language (HDL) such as: automatic Simulink to HDL, automatic C/C++ to HDL or directly by a HDL implementation. In addition, the concept of Hardware in the loop is introduced where the block is actually run on field programmable gate array (FPGA) hardware. The platform allows the use of the FPGA as a hardware accelerator or coprocessor. Different tradeoffs in algorithm hardware implementations can be explored such as: signal throughput, floating to fixed point conversion, hardware resources, silicon area estimates, power consumption, maximum operating frequency, and signal to quantization noise ratio.