This paper presents an improved StrongARM latch comparator, designed and simulated in 90nm and 32nm CMOS technologies. The proposed design provides an improvement of 7% in energy efficiency, 14% in speed and an average reduction of 41% in the clock feedthrough, compared to the conventional design. The new architecture also minimizes the area by reducing the required transistors needed for the enhanced performance.
We investigate the use of a lateral IMPAT? diode built in 0.25" CMOS technology as a high frequency power source. These diodes are monolithically integrated in coplanar waveguides and characterized by S-parameter measurements from 40 MHz to 110 GHz. These measurements show excellent agreement with predictions of theoretical models. To our knowledge, this is the first such structure built in a standard CMOS technology.
In this paper, we propose a forward body biasing technique to enhance the performance of the StrongARM comparators. We apply this technique, which is mainly based on clocked tuning of the threshold voltage of the NMOS cross-coupled transistors, to different architectures, namely: Kobayashi, Razavi, and Improved StrongARM comparators. The circuits are simulated in the standard 65nm CMOS technology and performance improvement of up to 20.8% has been achieved while maintaining the same energy loss.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.