We developed a novel Monte Carlo simulation model to investigate the line width dependence of the transport properties of multi-layered graphene nanoribbon (GNR) interconnects with edge roughness. We reported that the line width dependence of carrier mobility decreases significantly as the magnitude of the edge roughness gets smaller, which agrees well with experiments. We also discussed the influence of the inelasticity of edge roughness scatterings, inter-layer tunneling, and line width dependent band structures on the line width of the GNR interconnects.
A 75 mm low power 64 Gb MLC NAND flash memory capable of 30 MB/s program throughput and 533 MB/s data transfer rate at 1.8 V supply voltage is developed in 15 nm CMOS technology. 36% power reduction from 3.3 V design is achieved by a new pumping scheme. New low current peak features reduce a multi-die concurrent programming peak by 65% for 4-die case, and an erase verifying peak by 40%, respectively. Nanoscale transistors reducing bit-line discharge time by 70% is introduced to improve performance.Index Terms-NAND flash memory, low power, low peak current, nanoscale transistor, peak power management, smart pumping power control, 15 nm.Mario Sako was born in Gifu, Japan, in 1979. He received the B.E. degree in electronic engineering from Nagoya Institute of Technology and M.E. degree in electronic engineering from Nagoya University, Aichi, Japan, in 2003 and 2005, respectively. In 2005, he joined the Memory Design Department, Toshiba Corporation, Yokohama, Japan. Since 2008, he has been working on the circuit design of NAND flash memories.
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