We introduce the wafer-level compliant bump for chip stacking and 3-dimensional integration systems with high-density area bump interconnections. An inter-chip connection of up to 10,000 bump connections is demonstrated, where the bump size/pitch is 10 µm/20 µm. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in a device even when the bump bonding is performed directly on the device.
The drain breakdown voltage of n-channel silicon-on-insulator (SOI) metal oxide semiconductor field-effect transistors (MOSFETs) was found to decrease with the application of uniaxial tensile strain along the channel. The decrease in drain breakdown voltage was found to depend on the direction of the strain applied with respect to the current flow. To investigate the mechanism of this phenomenon, the influence of uniaxial tensile strain on built-in potential at the source junction and on impact ionization was investigated using an SOI lateral diode and bulk MOSFET. Uniaxial strain was induced by mechanically applying bending deformation to the chip using a cantilever structure. Built-in potential at the source junction remained unchanged. Impact ionization rate at the drain edge of MOSFET was found to increase with increasing uniaxial tensile strain. This increase in impact ionization rate is shown to be the cause of the reduced drain breakdown of SOI MOSFET in the presence of uniaxial strain.
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