A 64KBIT DYNAMIC MOS RAR.1, capable of 20011s access time and 150mW power dissipation, has been developed using a single transistor cell and a single-level polysilicon gate process. The 64K RAM is organized as 16-kwords x 4 bits. All clocks, input and output signals are TTL compatible. The number of refresh cycle is chosen to be 128, as in the case of 16K RAMS. Figure 1 shows the block diagram of the 64K RAM, which is drawn on the microphotograph. It includes memory matrix, sense circuits, address buffers, decoders, timing generating circuits and output buffers. The 64K RA31 is divided into four 16K blocks.A sense circuit array is placed in the center of each 16K block to maintain a balanced configuration. Each o f two nodes of a sense circuit is connected to 64 memory cells. Figure 2 shows the sense circuitry which consists of sense circuit, memory cells and two dummy cells. This sense circuit is very sensitive and can detect a signal of less than 2 30mV. Details of this sense circuit have been previously reported'". Dimensions of the single-poly cell are l 4 p m x 15pm. The bit line signal transmitted from a memory cell has been designed t o be f l00mV in the worst case. Therefore, the sense circuit can operate with sufficient margine. The sense circuit is not only very sensitive, but also low power dissipating, 80pW/circuit, due to its dynamic operation.As the MOS FET channel length decreases, VDD a n d v t h become lower and the Vth approaches TTL low lcvcl, so that there is a very small noise margin. The level detecting circuit and its waveform appears in Figure 3. An address buffer, that utilizes the level detecting circuits, has been used in the 64K RAM: Figure 4. It consists of address input. amplification, acceleration and buffer circuits. As the address buffer operates fully dynamically, it dissipates only ImWlcircuit at 500ns cycle time. Moreover, it has TTI, compatibility, in spite of low threshold voltage (0.8V), through adoption of the level dctecting circuit. In the 64K RAM, this level detecting circuit is used not only as an interface circuit to TTL, but frequently as a level detecting circuit within timing generating circuits. Short channel MOS FETs cause a decrease in junction and gate oxide breakdown voltages and punch through voltage and lead to a decrease in de supply voltages and MOS FET threshold voltage. The investigation of delay-power products, concerning short channel MOS FET inverter circuits, was also accomplished, to improve the circuit performance. These restrictions and investigations lead to the adoption of low dc supply voltages; 7V and -2V. Features of the MOS transistor are 2 p m effective __ channel length, 500A gate oxide thickness, 0.25pm junction depth and 0.8V threshold voltage at 1V drain voltage. The 64KRAM has been fabricated utilizing a 2pm-rule VLSI fabrication technology; Figure 1. The measured dependence of access time and power dissipation of the 64K RAM o n VDD are shown in Figure 5 . Key device characteristics of the 64K RAM arc summarized in Table 1. The technol...
Scanning Auger electron spectroscopy observation revealed that a patch of Ag thin film with a thickness of several monolayers spread on the cathode side over the clean surface of Si(111) 7×7 with the application of dc current to the Si substrate. The spread-out layer had the constant thickness of 1.0 monolayer (=7.8×1014 atom/cm2) with √3×√3 structure. On the anode side the edge of the patch made no significant movement but a mixed phase of √3×√3 and 3×1 with a thickness of 0.8 monolayer appeared and extended from the edge toward the cathode. The mass transport was correlated with changes in the structure of the overlayer.
A novel scanning device utilizing the mino rity carrier storaee effect in a bipolar transis tor ( MCSD ) is presented. MCSD principle opera tion and imaging application are mentioned. MCSD has a working frequency range that depends on the characteristics of the transistors in use, that is, 0.6 -1014Hz ( life time TF= 50 nsec ) or 0. 1 -0.5 MHz ('tF=600 nsec). The computed working range also shows the essential influence of the time constants of transistors. An integra ted MCSD with 64 stages and 64 photo-transistors is discussed. EiTRODUCTION The scanner is important for devices sequen tially driving photo-sensing elements, light-emi tting diodes and so on. Conventional scanners, composed of more than 4 components, are limited by the decrease in the packing density of these devices(l). Bucket-brigade scanners are limited in the number of integrated stages because of their transfer inefficiency(2). To overcome this problem, it is necessary to reduce the number of components of each stage of the scanner without transfer inefficiency. MCSD comprises only one transistor or two per one stage, and has no transfer inefficiency. In this paper, basic MCSD operation and results and diffi culty in imaging application are reported. BASIC OPERATION Principle of operation Figure 1 shows measurements of the minority carrier storage effect in a bipolar transistor. This is the collector current response when bias is applied between the collector and emitter with the base floated after the collector junction was forward biased. It is observed that the response time Ts is almost constant,even if the recovering collector current (Ir) is varied to be larger than the forward collector current(If). Response time Ts is given by Eq.(l). Ts 'CF 1 1 If 1 _ o.N 0.1 In( 1 + 1 -o.N Ir ( 1) 63 where
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