Integrated circuit (IC) technology is changing in multiple ways: 193i to extreme ultraviolet exposure, planar to nonplanar device architecture, from single exposure lithography to multiple exposure and directed selfassembly (DSA) patterning, and so on. Critical dimension (CD) control requirement is becoming stringent and more exhaustive: CD and process windows are shrinking, three-sigma CD control of <2 nm is required in complex geometries, and a metrology uncertainty of <0.2 nm is required to achieve the target CD control for advanced IC nodes (e.g., 14, 10, and 7 nm nodes). There are fundamental capability and accuracy limits in all the metrology techniques that are detrimental to the success of advanced IC nodes. Reference or physical CD metrology is provided by atomic force microscopy (CD-AFM) and TEM while workhorse metrology is provided by CD-SEM, scatterometry, and model-based infrared reflectrometry (MBIR). Precision alone is not sufficient for moving forward. No single technique is sufficient to ensure the required accuracy of patterning. The accuracy of CD-AFM is ∼1 nm and the precision in TEM is poor due to limited statistics. CD scanning electron microscopy (CD-SEM), scatterometry, and MBIR need to be calibrated by reference measurements for ensuring the accuracy of patterned CDs and patterning models. There is a dire need for a measurement with <0.5 nm accuracy and the industry currently does not have that capability with inline measurements. Being aware of the capability gaps for various metrology techniques, we have employed data processing techniques and predictive data analytics, along with patterning simulation and metrology models and data integration techniques to selected applications demonstrating the potential solution and practicality of such an approach to enhance CD metrology accuracy. Data from multiple metrology techniques have been analyzed in multiple ways to extract information with associated uncertainties and integrated to extract the useful and more accurate CD and profile information of the structures. This paper presents the optimization of scatterometry and MBIR model calibration and the feasibility to extrapolate not only in design and process space but also from one process step to a previous process step. A well-calibrated scatterometry model or patterning simulation model can be used to accurately extrapolate and interpolate in the design and process space for lithography patterning where AFM is not capable of accurately measuring sub-40 nm trenches. The uncertainty associated with extrapolation can be large and needs to be minimized. We have made use of measurements from CD-SEM and CD-AFM, along with the patterning and scatterometry simulation models to estimate the uncertainty associated with extrapolation and the methods to reduce it. For the first time, we have reported the application of machine learning (artificial neural networks) to the resist shrinkage systematic phenomenon to accurately predict the preshrink CD based on supervised learning using the CD-AFM data. ...
Conventional approaches to CMP planarity and uniformity often include the optimization of carrier zone pressure, platen/carrier rotation, slurry flow, conditioning sweep profile etc. Advances in CMP equipment technologies have also enabled new possibility such as multi-zone carrier pressure control through APC for within-wafer non-uniformity (WiWNU) reduction. Other widely-adopted approaches include the use of high-selectivity of slurries to “stop dead” on the final layer of interests without creating excessive local topography due to oxide erosion. While all the above approaches prove effective to certain degree, they are, by nature, wafer-level to sub wafer-level processes. As a consequence, it is difficult for them to differentiate between adjacent chips locally, for example, and correct the non-uniformity to the range of a few nanometers across the wafer as required by RMG module for 22 nm technology nodes and beyond. In this contribution, a novel planarization scheme for RMG is presented to enable nano-scale gate height uniformity control across all dies on 300 mm wafers. The new scheme begins with conventional high-selectivity CMP process (pass-1 W-CMP) to remove overburden and polish the gate height down to a few nanometers thicker than the final target, followed by all-chip gate height measurement on all wafers. Then the gate height data are fed forward to a GCIB tool, where location-specific process (LSP) takes place to trim the oxide down to a pre-determined target, chip by chip. This is followed by a final tungsten touch-up CMP process with high tungsten-to-oxide selectivity to level off the protruded metal patterns and drive the gate height to final target.
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