Oxidation characteristics of nonpatterned and patterned poly-SiGe layers were evaluated to confirm the feasibility for the application of poly-SiGe to the gate electrode. Characterization of poly-SiGe after oxidation was performed using atomic force microscopy ͑AFM͒, X-ray photoelectron spectroscopy ͑XPS͒, cross-sectional transmission electron microscopy ͑TEM͒, and energy-dispersive X-ray spectroscopy ͑EDS͒. The oxide thickness on poly-SiGe layer increased with increasing Ge content, while that on poly-SiGe ͑Ge 20%͒ sample was comparable to that of poly-Si ͑Ge 0%͒. When the Ge content was more than 40%, two different oxide layers were observed on poly-SiGe. Intensive analyses revealed that the oxide layers were composed of SiO 2 -rich mixed oxide (SiO 2 ͑GeO 2 ͒) and GeO 2 -rich mixed oxide (GeO 2 ͑SiO 2 ͒͒. For the patterned poly-SiGe sample, the oxidation characteristics were similar to those of nonpatterned sample. The best sidewall oxide profile was obtained in poly-SiGe ͑Ge 20%͒ sample. Because the sidewall oxide thickness is too thick for poly-SiGe sample with more than 40% of Ge, poly-SiGe ͑Ge 20%͒ is believed to be the most suitable candidate for gate electrode material.
It is the first time that the high-k/metal gate technology was used at peripheral transistors for fully integrated and functioning DRAM. For cost effective DRAM technology, capping nitride spacer was used on cell bit-line scheme, and single work function metal gate was employed without strain technology. The threshold voltage was controlled by using single TiN metal gate with La 2 O 3 and SiGe/Si epi technology. The optimized DRAM high-k/metal gate peripheral transistors showed current gains of 65%/55% and DIBL improvements of 52%/46% for nMOSFET and pMOSFET, respectively. The results in process yield, performance, and reliability characteristics of the technology on 4Gb DRAM have shown that the gate-first high-k/metal gate DRAM technology can be regarded as one of the major candidates for next-generation low power DRAM products.
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