A T-shaped-gated ͑T-gate͒ poly-Si thin-film transistor ͑TFT͒ with symmetric vacuum gaps has been proposed and fabricated simply with a selective-etching technique and an in situ vacuum encapsulation. The proposed TFT has demonstrated a higher maximum on-off current ratio and superior reliability compared to the conventional TFTs. This is attributed to the resulting offset region and vacuum gap to reduce the off-state leakage current and improve the hot-carrier reliability, while the extra subgate serves to induce an inversion layer at the offset region to maintain the on current during the on state. Therefore, such a T-gate poly-Si TFT is very suitable for manufacturing and applications in active-matrix flat panel electronics.
We have successfully proposed a patterned P3HT thin-film transistor with cross-linked PVP as a passivation material which was cured at low temperature. The active P3HT layer was isolated via photolithographic technique and O 2 plasma RIE etching process. In this method, the leakage current could be reduced effectively compared with that of non-patterned device. Although the mobility was degraded 40 %, but the on/off ratio was significantly improved by over three orders and also the subthreshold swing was compatible with the amorphous Si-TFTs (~1.5 V/decade). Moreover, we also employed this low temperature curing PVP (120 0 C) films as the gate dielectrics which exhibited excellent insulating property with high on/off ratio 1.58×10 4 and good subthreshold swing 1.66 V/decade.
The gate‐all‐around (GAA) fin‐like poly‐Si TFTs (FinTFTs) with multiple nanowire channels (MNCs) have been fabricated using a simple process to demonstrate high performance electrical characteristics. The fin‐like nanowire (NW) channel with high body thickness‐to‐width ratio (TFin/WFin), approximately equals to one, was realized only with a sidewall‐spacer formation. The unique suspending MNCs were also achieved to build the GAA structure. By the way, the GAA‐MNC FinTFTs showed outstanding three‐dimensional gate controllability and excellent electrical characteristics, which revealed a high ON/OFF current ratio (> 108), a low threshold voltage, a steep subthreshold swing, a near‐free drain‐induced barrier lowering and a good reliability. Therefore, such the high‐performance GAA‐MNC FinTFTs are very suitable for the applications in the system‐on‐panel (SOP) and three‐dimensional (3D) circuits.
A novel poly-Si field-enhanced nanowire (FEN) TFT memory with the TiN-hafnia-nitride-vacuum-silicon (THNVAS) structure fabricated simply via a sidewall spacer formation has been presented. The THNVAS devices with superior memory performance were demonstrated by introducing the hafnia as blocking oxide and the vacuum, the lowest-k in nature, as tunneling layer. According to the simulation results, the memory device with oxide/nitride/vacuum gate dielectric exhibited a higher local electric-field of 4.72 x 10(7) V/cm as compared to 2.55 x 10(7) V/cm for the conventional oxide/nitride/oxide counterpart. In addition, the electric-field of tunneling layer could be further increased to 7.06 x 10(7) V/cm while the blocking oxide was substituted for hafnia. The experimental data showed that THNVAS possessed a greater threshold voltage shift of 3.75 V in 10 ms at V(GS) = 12 V, whereas the shift only 2.5 V for THNOS ones. These considerable improvements for THNVAS devices could be attributed to the evident field enhancement across the vacuum tunneling layer. Furthermore, owing to the empty feature of vacuum tunneling layer, the THNVAS demonstrated much-improved endurance performance and preferable data retention property. Hence, such excellent characteristics of THNVAS will be an attractive nonvolatile memory for future system-on-panel and 3-D Flash applications.
In this study, traditional bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) (BCD) technology, which is designed for only lateral bipolar (Bipolar, 12 V BVCEO and 25 V BVCBO), complementary metal oxide semiconductor (CMOS, 1.2 V threshold voltage) and double diffused metal oxide semiconductor (DMOS, 40 V breakdown voltage) transistors on the bulk silicon wafer, has been successfully utilized directly in silicon on insulator lateral double diffused metal oxide semiconductor (SOI LDMOS) for the first time without changing any trial parameters. To simultaneously display the characteristics of high-power, high-speed and high-frequency, the results of output characteristics, switch and microwave performance must be moderate instead of optimum. In addition, according to the experimental results, it is proved that Bulk-BCD technology simultaneously enables high-speed, high-frequency and high-blocking-voltage applications–such as those in high-voltage integrated circuit switches (ns-range) and RF power amplifiers (MHz range to GHz range)–using a SOI wafer.
A novel T-shaped-gated (T-Gate) polycrystalline silicon thin-film transistor (poly-Si TFT) with in-situ vacuum gaps has been proposed and fabricated with a simple process. The T-Gate structure is formed only by a selective undercut-etching technology of the Mo/Al bi-layers. Then, vacuum gaps are in-situ embedded in this T-Gate structure subsequent to capping the SiH 4 -based passivation oxide under the vacuum process chamber. The proposed T-Gate poly-Si TFT has demonstrated to suppress the short-channel effects by simulated and measured characterization.It is attributed to the undoped offset region and vacuum gap to reduce the maximum electric field at drain junction..
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