This paper reports tri-gate sub-100 nm In 0.53 Ga 0.47 As QW MOSFETs with electrostatic immunity of S = 77 mV/dec., DIBL = 10 mV/V, together with excellent carrier transport of g m,max > 1.5 mS/µm, at V DS = 0.5 V. This result is the best balance of g m,max and S in any reported III-V MOSFETs. In addition, extracted compact model parameter including (μ 0 = 760 cm 2 /V-s and peak v x0 = 1.6×10 7 cm/s) indicate that InGaAs Tri-Gate MOSFETs would be a viable pathway to sub-10nm technology node.Introduction: Indium-rich InGaAs channel materials are a candidate for future low-power logic applications [1-2]. Tri-gate transistor architecture has been successfully demonstrated for improved electrostatics in Si MOSFETs [3][4] and most recently in III-V MOSFETs [5][6]. However, most of III-V tri-gate devices reported so far have shown wide fin geometry or poor interface quality between high-k dielectric and sidewall of etched Fin, failing to demonstrate performance and electrostatics benefit over the best ultrathin-body (UTB) planar III-V QW MOSFETs [7][8]. In this work, tri-gate In 0.53 Ga 0.47 As QW MOSFETs with bi-layer high-k dielectrics of Al 2 O 3 /HfO 2 are reported. In particular, L g = 60 nm tri-gate In 0.53 Ga 0.47 As QW MOSFETs with narrow fin width (W fin ) of 30 nm, fin height (H fin ) of 20 nm and EOT < 1 nm, yield excellent electrostatic integrity and performance benefit over UTB planar III-V MOSFETs, such as S = 77 mV/dec., DIBL = 10 mV/V, g m > 1.5 mS/µm and v ox = 1.6ⅹ10 7 cm/s. This result is significant because it shows that excellent electrostatics and performance can be achieved with high-k oxides directly on an etched tri-gate MOSFETs down to L g = 60 nm.
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