Atomic layer deposited (ALD) high-dielectric-constant (high-k) materials have found extensive applications in a variety of electronic, optical, optoelectronic, and photovoltaic devices. While electrical, optical, and interfacial properties have been the primary consideration for such devices, thermal and mechanical properties are becoming an additional key consideration for many new and emerging applications of ALD high-k materials in electromechanical, energy storage, and organic light emitting diode devices. Unfortunately, a clear correspondence between thermal/mechanical and electrical/optical properties in ALD high-k materials has yet to be established, and a detailed comparison to conventional silicon-based dielectrics to facilitate optimal material selection is also lacking. In this regard, we have conducted a comprehensive investigation and review of the thermal, mechanical, electrical, optical, and structural properties for a series of prevalent and emerging ALD high-k materials including aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), hafnium oxide (HfO 2 ), and beryllium oxide (BeO). For comparison, more established silicon-based dielectrics were also examined, including thermally grown silicon dioxide (SiO 2 ) and plasma-enhanced chemically vapor deposited hydrogenated silicon nitride (SiN:H). We find that in addition to exhibiting high values of dielectric permittivity and electrical resistance that exceed those of SiO 2 and SiN:H, the ALD high-k materials exhibit equally exceptional thermal and mechanical properties with coefficients of thermal expansion ≤ 6 × 10 -6 / • C, thermal conductivites (κ) of 3-15 W/m K, and Young's modulus and hardness values exceeding 200 and 25 GPa, respectively. In many cases, the observed extreme thermal/mechanical properties correlate with the presence of crystallinity in the ALD high-k films. In contrast, some of the electrical and optical properties correlate more strongly with the percentage of ionic vs. covalent bonds present in the high-k film. Overall, the ALD high-k dielectrics investigated concurrently exhibit compelling thermal/mechanical and electrical/optical properties. The drive to reduce gate leakage currents in highly scaled complementary metal-oxide-semiconductor (CMOS) transistors has led to the exploration and development of a wide variety of high-dielectricconstant (high-k) materials to replace silicon dioxide (SiO 2 ) as the insulating gate dielectric material.1-8 Many of these same high-k materials have found additional applications in future non-CMOS logic and memory storage products such as solid-state electrolytes in resistive switching devices, 9,10 tunnel barriers in spin-transport devices, 11 and as a ferroelectric in magnetoelectric devices. While electrical, physical, and thermodynamic properties have clearly been a key consideration in all of the above applications, thermal properties have become an additional important consideration for higk-k dielectrics as aggressive dimensional scaling of devices has created the need to dissipate ...
Beryllium oxide (BeO) is a wide band gap alkaline earth oxide material that has recently shown significant promise as a high-k dielectric material in Si and III-V metal–oxide–semiconductor field effect transistor devices. However, many of the basic material properties for BeO thin films utilized in these devices have not been reported or remain in question. In this regard, the authors report an investigation of the chemical, physical, electrical, and mechanical properties of BeO thin films formed via atomic layer deposition (ALD). Combined Rutherford backscattering and nuclear reaction analysis measurements show that ALD BeO thin films exhibit a low hydrogen content (<5%) and are nearly stoichiometric (Be/O ≅ 1.1 ± 0.05). Reflection electron energy loss spectroscopy measurements reveal a wide band gap of 8.0 ± 0.14 eV, and nanoindentation measurements show that ALD BeO has a high Young's modulus and hardness of 330 ± 30 and 33 ± 5 GPa, respectively.
Table 1 Comparison of potential sub-10 nm III-V device architectures Fig. 1 and 2 Schematic of ET-QW InAs MOSFETs and TEM images for L g = 50 nm ET-QW InAs MOSFETs with T QW = 5 nm. Note that 3-nm Al 2 O 3 was used as a gate insulator, together with MBE-grown 2-nm InP, leading to EOT = 2 nm. This paper reports Extremely-Thin-Body (ETB) InAs quantum-well (QW) MOSFETs with improved electrostatics down to L g = 50 nm (S =103 mV/dec, DIBL = 73 mV/V). These excellent metrics are achieved by using extremely thin body (1/3/1 nm InGaAs/InAs/InGaAs) quantum well structure with optimized layer design and a high mobility InAs channel.The ETB channel does not significantly degrade transport properties as evidenced by g m >1.5 mS/μm and v inj = 2.4 10 7 cm/s. Abstract:Introduction: The superior electron transport properties of III-V materials enable an attractive route to V dd scaling at sub 10 nm nodes. Extremely thin (ET) architectures (finFET or planar ETB) are a choice of technology at these geometries to maintain electrostatic integrity and control short channel effects (SCE) [1-3]. However, thinning down a channel degrades carrier transport properties. For the first time, we report ETB-QW L g = 50 nm InAs MOSFETs that exhibits excellent SCE control and favorably benchmarks an injection velocity (v inj ) against other III-V and Si devices. This comparison demonstrates that channel thickness can be scaled to at least 5 nm and the v inj advantage over Si maintained, demonstrating a potential scaling pathway to sub 10-nm technology node.Experimental: Table 1 as a motivation of this work compares different device architectures that can be considered for aggressively scaled III-V devices for future logic applications. The electrostatic control provided by ET-QW single gate devices may not be sufficient for sub-10nm nodes, but this architecture provides an excellent test structure to investigate the potential electron transport of multi-gate device with similar body/fin/nanowire width. Figs. 1 sand 2 show a cross-section of the device structure and corresponding TEM images of an L g = 50 nm device. MBE-grown 2-nm InP insulator was used to reduce access resistance and improve charge control, EOT and immunity to short channel effects as well as to improve D it [3].Extremely-Thin-Body of In 0.53 Ga 0.47 As/InAs/In 0.53 Ga 0.47 As (1/3/1nm) composite channel with inverted Si δ-doping and 5 nm In 0.52 Al 0.48 As spacer was chosen to improve carrier transport, electron confinement in the channel and electrostatic integrity. In a calibration structure, the Hall mobility was 8,400 cm 2 /V-s with n s,ch = 9.4 x 10 11 /cm 2 at 300 K. This is only about 24 % lower than the value obtained in a 10 nm thick In 0.7 Ga 0.3 As HEMT heterostructure [4], revealing that the use of 3-nm thin InAs sub-channel was effective in mitigating a degradation of carrier transport property.In 1D self-consistent Schrodinger-Poisson calculation for T QW = 5 nm epi structure, as the channel is thinned down, the carrier concentration in the channel at the acces...
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