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International audienc

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Two-dimensional numerical simulations indicate that a surface-potential bending greater than the Si-film Fermi potential is required to reach the threshold condition for the near-intrinsic thinfilm SO1 MOSFET's. Additionally, both n-and p-type SO1 films result intrinsic state and fully depleted condition. The threshold voltages of these devices are mainly dependent on the work function of gate ma-process complexity and cost. Further shrinkage in device dimensions may require a reduction in power supply voltage. The device threshold voltage has to be scaled acity. As a Rsult of reducing the threshold voltage, the offstate leakage current is increased. in approximately the Same device threshold voltage when in the near-cordingly to maintain the gain in current driving capabi1terial. High-performance submicrometer near-intrinsic thin-film SO1 complementary MOSFET's with balanced threshold voltages of about 0.4 V (negative for PMOSFET's) are achievable with proper selection of gate material and back-gate bias. The devices are relatively insensitive to process variations and short-channel effects when compared to their bulk silicon counterparts. For very thin (less than 100 nm) SO1 films, drain-induced barrier lowering (DIBL) is not sufficient to cause degradation of threshold voltage or punchthrough behavior in the submicrometer region. For relatively thick (greater than 100 nm) SO1 films, DIBL becomes more pronounced but can be suppressed by a proper back-gate bias. The simulated front-gate linear transconductance remains nearly constant up to about loi5and then falls off rapidly with increasing doping concentration because of mobility degradation. The subthreshold slope increases with decreasing channel length, increasing SO1 film thickness, and increasing drain voltage as a result of DIBL, but the increase is small for very thin SO1 films.