This paper presents a hardware implementation of multilayer feed forward neural networks (FFNN) using Field Programmable gate arrays (FPGAs). In spite of huge improvements in FPGA densities, the number of multipliers in a NN limits the size of the network that can be implemented using a single FPGA and the NN applications are not made commercially viable. The proposed implementation is aimed at reducing the resource requirements, without much compromise on the speed, so that a larger NN can be realized on a single chip at a lower cost. The parallel processing of the layers in an NN has been exploited in this paper to implement larger NNs. An efficient and fast carry look-ahead adder and Booth multiplier are the essential building blocks of the processing elements to perform parallel computation in the neural network. The activation function is implemented using piecewise linear approximation. In this work, a 2-2-1 multilayer feed forward neural network is implemented with different fixed point representation. The hardware resources consumed and the results obtained are presented.

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In this paper, design and FPGA (Field Programmable Gate Array) implementation of embedded system for time based IDEA encryption is presented. Presently available encryption systems, suffer from Brute Force attack in which all key combinations are tried out to find the correct key. In such a case, the time taken for breaking the code depends on the system used for cryptanalysis. In the proposed system, time is used as a second dimension of the key. That is, the correct key entered at the correct time is needed for proper decryption. The proposed scheme uses a dynamically varying number of shifts for both encryption and decryption thereby the system needs to wait till that time and this forms the time based key input. Hence, the possibility of brute force attack is minimized and is free from the system capability. IDEA encryption algorithm is taken as the base and time factor is implemented as a second dimension of the key. The proposed system adds complexity to the IDEA encryption algorithm by including the time as a second dimension besides increasing the time required for cryptanalysis. As the proposed system needs concurrent execution and real time processing, the system is implemented using Altera Stratix III FPGA and the results are presented. General TermsSecurity