FPGA based asynchronous pipelined multiplier with intelligent delay controller

Prabakar, T.N.; Lakshminarayanan, G.; Anilkumar, K.K.

doi:10.1109/socdc.2008.4815633

Cited by 8 publications

(3 citation statements)

References 7 publications

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“…The delay is defined considering the critical path of each stage. Different architectures have been proposed for the linear pipeline design style [36][37][38][39] . However, these pipeline architectures are generally focused on VLSI implementations, employing full-custom control 37 .…”

Section: Bundled-data Asynchronous Pipeline Architecturementioning

confidence: 99%

“…However, these pipeline architectures are generally focused on VLSI implementations, employing full-custom control 37 . FPGA-oriented pipelines have been proposed, but either complex delay mechanisms are used 38 or the operation in the fundamental-mode is not observed 39 . Mousetrap is an asynchronous pipeline architecture based on logic gates which can be implemented in FPGA and has good performance (see Fig.…”

Section: Bundled-data Asynchronous Pipeline Architecturementioning

confidence: 99%

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Design of DES encryption algorithm as bundleddata asynchronous pipeline using FPGA

Silva¹,

Oliveira²,

Batista³

2020

RBAV

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Currently, digital systems that are able to meet major security restrictions are increasingly being demanded, both in the military and in commercial areas. Data security can be achieved by cryptographic algorithms. An important encryption algorithm known as data encryption standard (DES) was implemented in field programmable gate array (FPGA) in different synchronous architectures. In this paper, we have proposed the implementation of the DES algorithm in FPGA, in the asynchronous pipeline style. Compared to the implementation in FPGA using two different project styles, the proposed asynchronous obtained the average increase of 14.9% in throughput and the average reduction of 66.3% in latency.

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Section: Bundled-data Asynchronous Pipeline Architecturementioning

confidence: 99%

Section: Bundled-data Asynchronous Pipeline Architecturementioning

confidence: 99%

Design of DES encryption algorithm as bundleddata asynchronous pipeline using FPGA

Silva¹,

Oliveira²,

Batista³

2020

RBAV

View full text Add to dashboard Cite

show abstract

“…The proposed asynchronous controller is named as "INTASYCON" (stands for INTelligent ASYnchronous CONtroller) which is an HDL based hardware module used to control the asynchronous data flow inside an asynchronous circuit [4] and [5]. The data manipulations inside the controller, as shown in Fig.…”

Section: Intasycon -I Based Asynchronous Pipelined Systemmentioning

confidence: 99%

Design and implementation of an Asynchronous Controller for FPGA Based Asynchronous Systems

Prabakar¹,

Lakshminarayanan²,

Anilkumar³

2010

IJCA

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In a clause of combinational circuits, the throughput can be increased, without (wave) pipelining, by introducing data dependent delay feature thus avoiding the worst case delay. That is, in circuits like multipliers and adders which are the basic building blocks of any DSP system; the processing delay can be varied according to the magnitude of the input data. This makes the circuit asynchronous and necessitates a controller to arbitrate the data. Systems like FIR filters, where a series of combinational multipliers are used, can be asynchronously pipelined with a controller regulating the data between stages. With this system level pipelining, speed of circuit level pipelining can be achieved provided the data are of low magnitude. In this paper, two controller architectures are presented to regulate the data flow between asynchronously pipelined stages. Firstly, as a stepping stone, Altera"s soft-core NIOS processor [1] is used and secondly, an exclusive asynchronous controller is designed using HDL. These controllers are designed to suit asynchronous implementation in conventional FPGAs, to effectively handle repeated data and to perform self-test. These controllers issue the control signals to the various dual edge triggered pipelined registers to process the data in both the edges for further improving speed. In the HDL version of the controller, programmable delays are generated by a "logic locked" high frequency counter without using delay elements. To verify the efficacy of these controllers 2 tap FIR filter is implemented using Braun array multipliers and adders. Thus, this approach consumes lower power and achieves data dependent throughput and also avoids the need for global clock signals and skew problems.

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A New Method for FPGA-Based 24x24-Bit Low-Power Multiplier

Xing¹,

Xing²,

Li³

2010

2010 International Conference on Multimedia Technology

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Through improving the existing coding algorithms, this paper presents a new coding algorithm, which reduces power dissipation in the way of reducing the number of partial product.Because the main operation of the multiplier is the sum of partial products, therefore, the reduction of the number of partial product can decrease the number of adder in multiplier, so the power dissipation can be decreased. The multiplier was given the results of simulation and test, and was compared with the multipliers which were designed with the existing coding algorithms, and the power dissipation was decreased by 3.5% and 8.4%.

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FPGA based asynchronous pipelined multiplier with intelligent delay controller

Cited by 8 publications

References 7 publications

Design of DES encryption algorithm as bundleddata asynchronous pipeline using FPGA

Design of DES encryption algorithm as bundleddata asynchronous pipeline using FPGA

Design and implementation of an Asynchronous Controller for FPGA Based Asynchronous Systems

A New Method for FPGA-Based 24x24-Bit Low-Power Multiplier

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