Introduction:In order for SO1 technology to be acceptable for future VLSI applications, it is important to understand how properties of the buried oxide (BOX) can impact SO1 device performance and reliability. Because the SIMOX buried oxide possesses several distinctly different characteristics from thermal Si02 [I] [2], a fundamental understanding of BOX conduction mechanisms is required.In this study, the electric-field, time, and temperature dependence of intrinsic SIMOX buried-oxide conduction has been characterized. Assymmetry was observed between positive and negative applied gate voltage. Two primary conduction regimes have been identified for both polarities: a high-field regime that appears to be due to Fowler-Nordheim tunneling with substantial apparent barrier-height lowering at both injecting interfaces, and a low-field regime likely due to time-dependent trapping current.Experimental Methodology: Single implant low-pinhole p-type SIMOX wafers were characterized in this study. The SIMOX process consisted of a 200keV 0 2 implantation performed at a substrate temperature of 600'C and an implant angle of 7' . The final dose was 1.8 x 10"cm2. The samples were then annealed a t 1310'C for 5 hours. The average top Si thickness is 200nm; the average BOX thickness, 386nm. The top silicon layer was degenerately doped with boron and mesa etched in order to form a set of 500pm x 500pm buried oxide capacitors. Dopant activation was achieved using a 30 minute, 950'C nitrogen anneal.A static current-density versus electric-field measurement technique was developed in order to allow independent measurement of the time and electric-field dependence of BOX conduction. (Potential measurement artifacts can exist with ramp/step voltage I-V BOX measurements). The static J-E technique consists of first performing a series of constant voltage/E-field measurements as a function of time for an identical set of BOX capacitors. This data is then replotted as a set of isochronal current-density versus electric-field characteristics (Figure 1). Note that a new capacitor is used for each different electric field and temperature value in order to miniinize the affect of any stress-induced BOX traps or interface damage. However, this also result in scatter in data due to device-to-device variation. For all data shown, the voltage polarity and current-flow direction are defined with respect to the substrate.
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