Using a statistical metrology framework to identify systematic and random sources of die- and wafer-level ILD thickness variation in CMP processes

Chang, E.; Stine, B.E.; Maung, T.; Divecha, R.; Boning, Duane S.; Chung, J.E.; Chang, Keh-Jeng; Ray, G.W.; Bradbury, D.R.; Nakagawa, O.S.; Oh, Soo‐Young; Bartelink, D. J.

doi:10.1109/iedm.1995.499247

Cited by 32 publications

(28 citation statements)

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“…Intra-die variation has only recently received appreciable attention, in part due to the need for a large amount of statistically meaningful data, and the prevailing belief that intra-die variation is inconsequential compared to lot-to-lot, waferto-wafer, and within-wafer variation. Our studies [4,6] and those elsewhere [1,3] have shown that this is not the case and that intra-die variation is often much larger or comparable to the other variational sources.…”

Section: Motivationmentioning

confidence: 75%

“…Furthermore, by looking at the spatial dependence of each factor type, geometric orientation versus spacing in this particular case, possible different physical and spatial dependencies can be highlighted. For example, (5) indicates that isolated features have a positive dependence on radial position while the stacked and fingered components have a negative dependence on radial position. The relatively low correlation coefficients illustrated in Table III may result from either a large random component inherent in the data and/or a more complex spatial dependence which is only properly formulated in a non-parametric sense.…”

Section: Figure 4 Several Extracted Wafer-level Variation Componentsmentioning

confidence: 99%

“…Key examples include critical line-width dimension variation in channel length or metal lines [1,2,3], and pattern planarization in chemical mechanical polishing [4,5]. Intra-die variation has only recently received appreciable attention, in part due to the need for a large amount of statistically meaningful data, and the prevailing belief that intra-die variation is inconsequential compared to lot-to-lot, waferto-wafer, and within-wafer variation.…”

Section: Motivationmentioning

confidence: 99%

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<title>Inter- and intra-die polysilicon critical dimension variation</title>

et al. 1996

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A methodology has been developed as part of a statistical metrology framework (1) to assess the relative range and distribution of intra-die, or die-level, polysilicon critical dimension variation as opposed to wafer-level, or inter-die, poly-CD variation; (2) to identify the key layout factors involved in poly-CD intra-die variation; and (3) to develop first-order semi-empirical models for poly-CD variation. A new approach utilizing multivariate analysis of variance methods is described to model the die-and wafer-level variation components. We show that pattern dependent variation is approximately twice as large as waferlevel variation. In addition, we find that spatial position plays a strong role: the first-order pattern dependent variation model (or die "signature") shows a strong dependence on spatial position across the wafer, and individual components of the model demonstrate different spatial position sensitivities.

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Section: Motivationmentioning

confidence: 75%

Section: Figure 4 Several Extracted Wafer-level Variation Componentsmentioning

confidence: 99%

Section: Motivationmentioning

confidence: 99%

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<title>Inter- and intra-die polysilicon critical dimension variation</title>

et al. 1996

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“…An example of a random component is that of threshold voltage variability due to random dopant fluctuations (Stolk et al, 1988); 2.2. systematic yield (including printability issues), related to systematic manufacturability issues deriving from combinations and interactions of events that can be identified and addressed in a systematic way. An example of these events is the variation in wire thickness with layout density due to Chemical Mechanical Polishing/Planarization (CMP) (Chang et al, 1995). The distinction from the previous yield is important because the impact of systematic variability can be removed by adapting the design appropriately, while random variability will inevitably impact design margins in a negative manner;…”

mentioning

confidence: 99%

Advanced Statistical Methodologies for Tolerance Analysis in Analog Circuit Design

Apolloni¹,

Bassis²,

Ciccazzo³

et al. 2011

Advances in Analog Circuits

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“…These variations can be the result of semiconductor process methods or environmental differences that are seen across the design based on layout. Examples of process induced systematic intra-die variation include 1) optical proximity effects that causes polysilicon features sizes such as Leff to vary as a function of local layout, 2) local wire densities that influence the inter-layer dielectric thickness achieved during chemical-mechanical polishing (CMP), and 3) spatial variation of Leff due to lens aberration across the die [4] [5] [6]. Many techniques have been used in manufacturing to reduce systematic intra-die variation.…”

Section: Introductionmentioning

confidence: 99%

Process and environmental variation impacts on ASIC timing

Zuchowski

Habitz

Hayes

et al.

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.

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IntroductionWith each semiconductor process node, the impacts on performance of environmental and semiconductor process variations become a larger portion of the cycle time of the product. Simple guard-banding for these effects leads to increased product development times and uncompetitive products. In addition, traditional static timing methodologies are unable to cope with the large number of permutations of process, voltage, and temperature corners created by these independent sources of variation. In this paper we will discuss the sources of variation; by introducing the concepts of systematic inter-die variation, systematic intra -die variation, and intra-die random variation. We will show that by treating these forms of variations differently, we can achieve design closure with less guard-banding than traditional methods.ASIC providers are typically responsible for the performance and yield of the devices they deliver. It is therefore common in the ASIC industry to require timing closure, as measured by a static timing analysis tool, at fast process and slow process timing corners. These corners are supposed to represent the maximum variation that is possible between any two die due to normal manufacturing tolerances. The definition of these fast and slow corners is usually done by moving all of the relevant process parameters (eg. channel length, threshold voltage, etc.) to some statistical limit and developing timing models with these process assumptions. It is also now common for ASIC providers to require timing sign-off assuming some amount of on-chip variation. This additional conservatism is added to account for the intra-die variations which can result in missed timings due to differential process variation (and therefore delays) on the clock and data paths. Environmental condition variations, such as end user voltage and temperature, are also accounted for by running additional static timing corners. In the recent past, these methods were sufficient to guarantee timing, and therefore yield, across the range of the normal manufacturing process window.With continued scaling of CMOS technology however, the numbers of relevant sources of variation and their magnitude have increased. In an attempt to account for this , additional static timing corners are being added to ASIC design flows to account for sources of variation that were previously ignored, such as mismatch between PFET on-current and NFET on-current due to threshold voltage variation.As additional sources of variation become important, either the total guard-band applied during static timing is increased, or the risk of impacting yield is increased. This comes about due to the different delay sensitivities of each path on a design and the inability of the currently available design automation tools to handle the unique sensitivities of each path on the chip without running 2 n timing corners, where n is the number of independent variables of interest. Some paths are predominately sensitive to metal delay while others are predominately sensi...

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Using a statistical metrology framework to identify systematic and random sources of die- and wafer-level ILD thickness variation in CMP processes

Cited by 32 publications

References 1 publication

<title>Inter- and intra-die polysilicon critical dimension variation</title>

<title>Inter- and intra-die polysilicon critical dimension variation</title>

Advanced Statistical Methodologies for Tolerance Analysis in Analog Circuit Design

Process and environmental variation impacts on ASIC timing

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