-This paper introduces a class of efficient linear-phase FIR decimators for attenuating the out-of-band noise generated by a high-order sigma-delta analog-to-digital modulator. The stopband attenuation of these decimators is more than 120 dB. The decimators contain no generd multipliers and a few data memory locations. thereby making them easily VLSI-realizable. This is achieved by using several decimation stages with each stage containing a small number of delays and arithmetic operations. Some of the stages have been constructed using low-order building blocks which are combined to give a selective filter using a few additional tap coefficients and adders. The output sampling rate of these decimators is the minimum possible one and the proposed decimators can be used. with very slight changes. for many oversampling ratios. hithermore. these deciniators attenuate highly the undesired out-of-band signal components of the input signal. thus significantly relaxing the anti-aliasing prefilter requirements.
A sigma-delta AID converter realization using two-stage 4th order modulator architecture and 5th order digital runningsum decimation filter is presented. The analog part of the converter consist of two cascaded second order modulators. Scaling is used between the sections in order to achieve modest requirements for component matching and integrator's gain and phase. A digital running-sum filter is used for the decimation to 4 f s or 2 f s . A dedicated 7 instruction filter processor is designed to perform the final decimation and 110-communication. The whole system operates on a single 5 V operation voltage. i I. JNTRODUCTIONWithin the past years, the technological improvements in digital VLSI circuits have dramatically increased the need of low cost high resolution A D and D/A converters. Completely new problems have risen for the analog interfaces in embedded systems because the A D conversion and the digital signal processing are on the same chip. The use of Nyquist rate A/D converters in such systems limits the resolution below 12 bits because most of the injected noise from the digital part is aliased into the baseband. In addition, their system integration is complex because effective antialias filters, high performance sample and hold circuits and jitterfree timing are needed.Many of the problems mentioned above can be solved using oversampling technique. Sigma-delta modulation is one of the most promising candidates because it combines oversampling and quantization noise shaping and digital filtering in order to achieve high performance with reduced analog circuit complexity. Sigma-delta converter has excellent linearity because it uses one-bit quantization. The noise coupling from the digital part is small because most of the noise is digitally filtered in the decimation filter. No sample and hold circuit is needed and a simple RC-filter prevents the aliasing of unwanted input signals. Moreover, most of the timing uncertainty becomes noise that spreads equally over the whole band and only a fraction of it lies in the baseband. This paper presents a high performance sigma-delta A D converter using 4th order modulator architecture [l], 5th order running-sum decimator and a dedicated filter processor (Figure 1). The filter processor provides complete programmability for the converter's amplitude response. No general multipliers are used which results small silicon area. The converter is designed in such way that it can be intcgrated using a low priced analog or digital CMOS process with capacitor structures. This makes it suitable for all kinds of high volume digital audio, telecommunication and instrumentation applications. The converter achieves theoretically 18-bit resolution for the audio band at 2.8 MHz sampling frequency as depicted in Figure 2. The measurements with the first prototype indicate that this limit can be achieved in practice by minor improvements in the prototype's analog hardware. 1 I M=32,64, 32 serial out -I.'igure 1. Block diagram of the sigma-delta converter. MODULATORThe 4th order ...
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