This paper describes a multi-speed digital cross-connect switching VLSI using innovative circuit techniques in dual port RAMs, and adopting 0.8pm CMOS technology. The five embedded dual port RAMS (four lkw X9b, one 256w X 18b), each achieved an access-time of 3.7ns and lOOmW power consumption at 38.88MHz operation.
Synchronous digital hierarchy (SDH) standardized in International Telecommunication Union-Telecommunication Standard Sector (ITU-T) applies a new multiplexing method using a pointer that indicates a tributary location in the SDH frame. The location of the SDH frame heads received from several lines is adjusted at interface circuits to facilitate the multiplexing process in the SDH equipment. Since the frame head locations of input signal differ from the output signal, pointer values are attached to the output signals. The pointer conversion of each tributary is performed independently of each other. Therefore the pointer values of tributaries transported on the same line might be different from each other after the conversion even if these values are the same. Hence large amounts of buffer memory would be required at the destination point to provide a transport service utilizing multiple virtual containers (VCs). This paper proposes a new pointer conversion method that keeps the pointer value differences unchanged between tributaries multiplexed in an SDH frame. This method allows multiple VC transport service to be provided.
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