A multi-speed digital cross-connect switching VLSI using new circuit techniques in dual port RAMs

Abstract

This paper describes a multi-speed digital cross-connect switching VLSI using innovative circuit techniques in dual port RAMs, and adopting 0.8pm CMOS technology. The five embedded dual port RAMS (four lkw X9b, one 256w X 18b), each achieved an access-time of 3.7ns and lOOmW power consumption at 38.88MHz operation.

A 200 Mhz 0.8μm BiCMOS Modular Memory Family Of DRAM And Multiport SRAM

“…Many multiport SRAM designs have dedicated read or write only ports and use single cndcd ccll access schemes [5,6,7]. Although single endcd cclls may offer some core density improvements whcn tailorcd to a spccific application, a fully differential cell provides superior read access times for a given cell area due to the improved speed attainable with differential sense schemes.…”