In this work we report on the elaboration and characterization of Ge1−xSnx nanowires synthetized by chemical vapor deposition (CVD) via vapor–liquid–solid (VLS) mechanism using GeH4 and SnCl4 as precursors. We have investigated tin incorporation in Ge as a function of experimental growth conditions such as growth temperature and Sn precursor partial pressure (PSnCl4/PGeH4 ratio). We have demonstrated Ge1−xSnx nanowires with Sn incorporation around 1 at.% in the core with a thin Sn‐rich shell with up to 10 at.% Sn well beyond the equilibrium solubility of Sn in bulk Ge.

We have investigated the impact of different wet treatments on the electrical performances of germanium–tin (GeSn)-based p-MOS capacitors with 10% Sn. Atomic force microscopy (AFM) showed the presence of Sn droplets for the degreased Ge0.9Sn0.1 surface, which were removed by HCl, HF, and HF:HCl treatments. On the other hand, (NH4)2S and NH4OH treatments were not fully able to remove these droplets. X-ray photoelectron spectroscopy (XPS) measurements confirmed AFM results and highlighted the efficiency of HF, HCl, and HF:HCl treatments in removing Ge and Sn native oxide, which was not the case with (NH4)2S and NH4OH. Nevertheless, XPS showed a reoxidation of the Ge0.9Sn0.1 surfaces a few minutes only after HF, HCl, and HF:HCl wet treatments. Therefore, another approach was tested. It consisted in using (NH4)2S to protect Ge0.9Sn0.1 surfaces from immediate reoxidation by creating a Ge0.9Sn0.1-S monolayer. Chemical depth profiles of Ge0.9Sn0.1/Al2O3 stacks were investigated using parallel angle resolved XPS (pAR-XPS), indicating a high quality interface when the Ge0.9Sn0.1 surface is cleaned previously by HF and then (NH4)2S. There was notably a lack of Sn or Ge diffusion into the Al2O3 layer. C–V characteristics combined with a custom-analytical model yielded a low interface trap density (D i t).

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Single silicon nanowire (SiNW) omega-gate field-effect transistors have been fabricated using a standard photolithography method on a Kapton flexible polyamide thin film attached to a sacrificial silicon substrate. SiNWs have been grown by the chemical vapor deposition method using a vapor-liquid-solid mechanism and gold as the catalyst. A key step for proper SiNW integration, Kapton surface flattening, was performed via an innovative method based on soap. Contrary to a previously reported integration process on flexible substrates, this flexible/rigid hybrid substrate is compatible with temperature as high as 400 • C, allowing the formation of low-resistive nickel silicide at the source/drain contacts. As a consequence, our devices can exhibit excellent electrical properties such as 22 cm 2 V −1 s −1 hole mobility, 10 5 I ON -to-I OFF ratio and subthreshold slope of about 340 mV dec −1 . These parameters can compete with those of organic transistors or in some aspects even exceeding electrical parameters of similar single SiNW transistors fabricated onto flexible substrates. In addition, after separation from the rigid silicon substrate, devices on Kapton experience a significant improvement in their performance, such as two orders of magnitude for I ON /I OFF ratio and halving the subthreshold slope. This flexible/rigid hybrid substrate, offering high chemical and thermal stability, as well as preserving good electrical features and even improving them, after detaching and transfering the polyamide layer to a plastic substrate, which opens up a new route for the integration of further nanostructures.

The impact of different interfacial layers (ILs) on the electrical performances of Au/Ti/HfO 2 /Ge 0.9 Sn 0.1 metal oxide semiconductor (MOS) capacitors is studied. Parallel angle resolved x-ray photoelectron spectroscopy measurements show that germanium diffuses into the HfO 2 layer when no IL is used. This results in an increase in the tin content at the interface and a high interface state density. We demonstrate that the use of an IL prevents germanium and HfO 2 intermixing and improves the electrical performance of MOS capacitors. Several ILs are studied such as alumina (Al 2 O 3 ) and plasma oxidized GeSn (GeSnO x ) prior to HfO 2 deposition. C-V measurements correlated with simulations made by a customized analytical model indicate an interface state density of 5 Â 10 11 eV À1 cm À2 for the HfO 2 /GeSnO x /Ge 0.9 Sn 0.1 gate stack. This result is promising for the integration of high mobility GeSn channels in CMOS devices.

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