THIS PAPER will describe a circuit design methodology for CMOS microcomputer LSIs that takes advantage of a hierarchical structure approach and includes a simplified circuit delay evaluation method that does not require computer simulation. An 8b, 30mW, CMOS microcomputer with 82,000 transistors was developed using this method. A regular, arranged structure was adopted t o provide VLSI chips with increased integration and flexibility. approaches:The proposed hierarchical design methodology involves two ( I )A CMOS logic circuit design having a hierarchical structure that is divided according to the operating speed of its functional blocks: for example, a kernal with a high speed clock and satellite blocks with relatively low speed clocks.within the required delay in each signal path, using simplified characteristic equations.( 2 ) Gate size optimization to minimize power dissipationThe power dissipation in a CMOS LSI is a function of C, f, and N. The load capacitor, C, increases in proportion t o the active area, S, while the transistor count, N, increases in proportion to 6 f is the operating frequency. To realize lowpower consumption and high performance simultaneously, it is important to limit the area operating at high frequency. Power reduction was achieved by dividing CMOS logic into a kernel and satellites is shown in Figure 1. Po and P are, respectively, power consumption for: ( a ) a high frequency clock applied t o the entire logic, which is not divided into a kernel and satellites, and ( b ) high and low frequency clocks applied to the kernel and its satellites.The propagation delay, Tpdi, of CMOS gate i can be approximated as Optimization of gate size is another key to power reduction.Here, Ci is the load capacitor, NIi is the number of inputs, W/L is the transistor size, and a1 to q are coefficients. Figure 2 shows a comparison of data as estimated using the equation with the results of circuit simulation. The propagation delay, Tpath, __ *HD 6301 Toshimasa KiharaHitachi, L td. Musashi, Japanof the signal path in the system is calculated as the gate delay sum Tpath = 2 Tpdi All parameters except W/L are taken from a lo@c diagram and floor plan. Thus, it is possible to determine the optimal transistor size for the required propagation delay, Tpath, for each signal path. Estimated data error is within ten per cent, and circuit evaluation time is reduced to less than 1/10 that of circuit simulation. Thus, this evaluation method can be used effectively to estimate Tpath, or for optimum transistor size determination of each gate along the paths.This method was applied to the design of a high-speed, low-power, 8b CMOS single-chip microcomputer". A schematic representation can be seen in Figure 3. This microcomputer is comprised of a kernel CPU, which is operated by a 4MHz clock, and satellite peripherals which are operated by a 2MHz clock. The kernel CPU includes a microprogram ROM with 16,000 transistors, and two sets of 8b execution units.Each execution unit can be operated simultaneously, and the ROM ac...
the hard disc, where the burst error-correcting code is frequently employed to im-The disc system is one of the areas of prove the reliability of the data. In the applications for the error-correcting code.implementation of the burst error-correct-For this purpose, a Fire code with the gener-ing code function in the VLSI chip for a c hard disc controller, the following pointsfrequently used. This paper considers the shortened Fire code, where the length of the code can be reduced according to the length of the record used. A decoding method suitable for VLSI is proposed. It is noted that the content of the feedback shift register with p(;c) as the divider returns to the original pattern when it is shifted by must be taken into consideration: (1) Scale of the hardware (chip area), (2) decoding time, (3) Frequency of utilization, and ( 4 ) easiness of design (logic, circuit and layout). for more than one information scale (record lengths), it is necessary to utilize ( 5 ) the decoding algorithm with the expandability.Especially, when a chip is utilized the period e of p ( x ) , and the speed is improved by ignoring the integer multiple shifts of e . This decoding method requires less hardware (i.e., shift registers and counters), and has the merits of easiness in design and expandability, according to the record length. The principle is expanded to the general cyclic code. The proposed decoding method is implemented on the hard disc controller (peripheral LSI for HDC 16 bit microcomputers). A 32-bit Fire code is used. For a typical record length of 512 bits in the disc system, the speed was comparable to that of the high-speed decoding.The error-correcting part is composed of 6700 Tr, which is 5.2% of the whole system (129 kTr). This figure demonstrates the practical usefulness of the proposed method in VLSI design.
A peripheral interface unit in a microcomputer control system fabricated by a standard n-channel silicon-gate enhancement/depletion MOS process is described. The unit, designed so as to meet customized requirements, has the capability of accepting analog and digital input, generating digital output, and multiplying. The analog input capability is made possible by an on-chip A/D converter using a constant slope approach. The use of a current source, a level shifter, and a threshold detector realizes a standard NMOS compatible converter with an external capacitor. The converter, which requires only a small die size, can perform a ten-bit conversion in 5 ms and has an input voltage range from 0 to 5 V with one positive power supply. Large-scale digital circuitry providing various logic functions with a specialized custom architecture is also included in the unit, which is 5.6 mm X 6.2 mm. This converter is especially suited for use in microcomputer control systems for specific consumer and industrial applications.
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