1983
DOI: 10.1109/isscc.1983.1156506
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Abstract: THIS PAPER will describe a circuit design methodology for CMOS microcomputer LSIs that takes advantage of a hierarchical structure approach and includes a simplified circuit delay evaluation method that does not require computer simulation. An 8b, 30mW, CMOS microcomputer with 82,000 transistors was developed using this method. A regular, arranged structure was adopted t o provide VLSI chips with increased integration and flexibility. approaches:The proposed hierarchical design methodology involves two ( I )A…

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