A circuit design methodology for CMOS microcomputer LSIs

Abstract

THIS PAPER will describe a circuit design methodology for CMOS microcomputer LSIs that takes advantage of a hierarchical structure approach and includes a simplified circuit delay evaluation method that does not require computer simulation. An 8b, 30mW, CMOS microcomputer with 82,000 transistors was developed using this method. A regular, arranged structure was adopted t o provide VLSI chips with increased integration and flexibility. approaches:The proposed hierarchical design methodology involves two ( I )A CMOS logic circuit design having a hierarchical structure that is divided according to the operating speed of its functional blocks: for example, a kernal with a high speed clock and satellite blocks with relatively low speed clocks.within the required delay in each signal path, using simplified characteristic equations.( 2 ) Gate size optimization to minimize power dissipationThe power dissipation in a CMOS LSI is a function of C, f, and N. The load capacitor, C, increases in proportion t o the active area, S, while the transistor count, N, increases in proportion to 6 f is the operating frequency. To realize lowpower consumption and high performance simultaneously, it is important to limit the area operating at high frequency. Power reduction was achieved by dividing CMOS logic into a kernel and satellites is shown in Figure 1. Po and P are, respectively, power consumption for: ( a ) a high frequency clock applied t o the entire logic, which is not divided into a kernel and satellites, and ( b ) high and low frequency clocks applied to the kernel and its satellites.The propagation delay, Tpdi, of CMOS gate i can be approximated as Optimization of gate size is another key to power reduction.Here, Ci is the load capacitor, NIi is the number of inputs, W/L is the transistor size, and a1 to q are coefficients. Figure 2 shows a comparison of data as estimated using the equation with the results of circuit simulation. The propagation delay, Tpath, __ *HD 6301 Toshimasa KiharaHitachi, L td. Musashi, Japanof the signal path in the system is calculated as the gate delay sum Tpath = 2 Tpdi All parameters except W/L are taken from a lo@c diagram and floor plan. Thus, it is possible to determine the optimal transistor size for the required propagation delay, Tpath, for each signal path. Estimated data error is within ten per cent, and circuit evaluation time is reduced to less than 1/10 that of circuit simulation. Thus, this evaluation method can be used effectively to estimate Tpath, or for optimum transistor size determination of each gate along the paths.This method was applied to the design of a high-speed, low-power, 8b CMOS single-chip microcomputer". A schematic representation can be seen in Figure 3. This microcomputer is comprised of a kernel CPU, which is operated by a 4MHz clock, and satellite peripherals which are operated by a 2MHz clock. The kernel CPU includes a microprogram ROM with 16,000 transistors, and two sets of 8b execution units.Each execution unit can be operated simultaneously, and the ROM ac...

Low Power Multicore Processors for Embedded Systems

“…Since the beginning of the microprocessor history, a processor especially for PC/servers had continuously advanced its performance while maintaining a price range from hundreds to thousands of dollars [11,12] . On the other hand, a single -chip microcontroller had continuously reduced its price, resulting in the range from dozens of cents to several dollars with maintaining its performance, and had been equipped to various products [13] . As a result, there was a situation of no demand on the processor of the middle price range from tens to hundreds of dollars.…”