The self-tuning regulator (STR) is a popular adaptive control algorithm. A high-performance computer is required for its implementation due to the heavy online computational burden. To extend STR for more realtime applications, a parallel hardware implementation on a low-cost reconfigurable computer is presented. The hardware was incorporated with multistage matrix multiplication (MMM) and trace technique to enhance the processing speed. This design was deeply pipelined to achieve high throughput. The algorithm was prototyped on a Xilinx field-programmable gate array (FPGA) device with a maximum operating frequency of 210.436 MHz. Application-specific integrated circuit (ASIC) implementation of STR was reported.
ACM Reference Format:Ananthan, T. and Vaidyan, M. V. 2013. A reconfigurable parallel hardware implementation of the self-tuning regulator.
Abstract:The wireless network is one of the most significant purposes behind the accomplishment of long range wireless communication. Frequent link failures are occurred in the sensor organised network due to obstruction, snags, message drop because of node energy depletion; Time to Live (TTL) lapsed and so forth. The total communication gets collapsed if there any lessening in the nature of correspondence or quality between the sensor nodes or from the sensor nodes to the sink nodes and this prompts to connection failures. To overcome the frequent link failures and to provide reliable data communication an Efficient SelfReconfiguration and Route Selection for Wireless Sensor Networks to mitigate link failures is proposed. E-SRRS scheme automatically senses the energy efficient nodes with reliable routes to improve and conserve the network performance. The simulation analysis for E-SRRS and the parameters such as throughput, transmission delay and energy consumption in the network is shown.
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