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This paper addresses the influences of device and circuit mismatches on paralleling the Silicon Carbide (SiC) MOSFETs. Comprehensive theoretical analysis and experimental validation from paralleled discrete devices to paralleled dies in multichip power modules are first presented. Then, the influence of circuit mismatch on paralleling SiC MOSFETs is investigated and experimentally evaluated for the first time. It is found that the mismatch of the switching loop stray inductance can also lead to on-state current unbalance with inductive output current, in addition to the on-state resistance of the device. It further reveals that circuit mismatches and a current coupling among the paralleled dies exist in a SiC MOSFET multichip power module, which is critical for the transient current distribution in the power module. Thus, a power module layout with an auxiliary source connection is developed to reduce such a coupling effect. Lastly, simulations and experimental tests are carried out to validate the analysis and effectiveness of the developed layout.

Thermal loading of power devices are closely related to the reliability performance of the whole converter system. The electrical loading and device rating are both important factors that determine the loss and thermal behaviors of power semiconductor devices. In the existing loss and thermal models, only the electrical loadings are focused and treated as design variables, while the device rating is normally predefined by experience with limited design flexibility. Consequently, a more complete loss and thermal model is proposed in this paper, which takes into account not only the electrical loading but also the device rating as input variables. The quantified correlation between the power loss, thermal impedance, and silicon area of insulated gate bipolar transistor (IGBT) is mathematically established. By this new modeling approach, all factors that have impacts to the loss and thermal profiles of the power devices can accurately be mapped, enabling more design freedom to optimize the efficiency and thermal loading of the power converter. The proposed model can be further improved by experimental tests, and it is well agreed by both circuit and finite element method (FEM) simulation results. Index Terms-Finite element method (FEM), insulated gate bipolar transistor (IGBT), power semiconductor, reliability, thermal model.

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This paper proposes a general physics-based model for identifying the parasitic capacitance in medium-voltage (MV) filter inductors, which can provide analytical calculations without using empirical equations and is not restricted by the geometrical structures of inductors. The elementary capacitances of the MV inductor are identified, then the equivalent capacitances between the two terminals of the inductor are derived under different voltage potential on the core. Further, a three-terminal equivalent circuit, instead of the conventional two-terminal equivalent circuit, is proposed by using the derived capacitances. Thus, the parasitic equivalent capacitance between the terminals and core are explicitly quantified. Experimental measurements for parasitic capacitances show a good agreement with the theoretical calculations. Index terms-Physics-based modeling, parasitic capacitance, medium-voltage, filter inductors, three-terminal equivalent circuit.This work is supported by MV-BASIC project (https://www.mvbasic.et.aau.dk/), which is co-funded by the