FinFET devices with source drain underlaps are attractive due to their high I on /I off ratios [1]. However, a thorough understanding of the device parasitics on underlap FinFET circuit performance is yet to be attained. In this paper, we report a new Extension Transistor Induced Capacitance Shielding (ETICS) phenomenon. Due to this phenomenon, the effective values of a FinFET logic gate's input and parasitic capacitances depend strongly on transition times of its terminal voltages. We show that understanding of this phenomenon is essential for circuit design.
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