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A four-level open-end winding induction motor drive (OEWIMD) is realised by feeding the open stator windings of a three-phase induction motor from either end with two-level voltage source inverters (VSIs). These VSIs are operated with unequal DC-link voltages, which are in the ratio of 2:1. This circuit configuration has the disadvantage of overcharging the DClink capacitor of the inverter operated with the lower input voltage. Decoupled space vector pulse-width modulation (DSVPWM) schemes, which were suggested in the previous literature to circumvent this problem, result in higher switching power loss in the dual-inverter topology. It is known that the discontinuous pulse-width modulation (PWM) schemes reduce the switching power loss. However, lack of structural symmetry of the power circuit renders it unwieldy to devise these PWM schemes. This study explores the applicability of discontinuous decoupled SVPWM (DDPWM) techniques for the four-level OEWIMD, without compromising on the waveform symmetries. With the aid of an improvised loss model, it is shown that these PWM schemes achieve the reduction of the overall loss of the four-level OEWIMD compared to the DSVPWM schemes. It has also been observed that one of the proposed DDPWM schemes result in reduced dv⁄dt in the motor phase voltages.

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Summary The four‐level open‐end winding induction motor (4‐L OEWIM) drive is constituted by two 2‐level voltage source inverters (VSIs), wherein their DC‐link voltages should be maintained in the ratio of 2:1. Owing to the unsymmetrical structure of the power circuit, the 4‐L OEWIM drive is plagued with the drawback of capacitor voltage imbalance. The DC‐link capacitor of one of the inverters, which is operated with the lower voltage level, that show the propensity of getting charged up by its higher voltage counterpart, belonging to the other inverter. In this article, two variants of space‐vector pulse width modulation (SVPWM) schemes are suggested for the 4‐L OEWIM drive. The suggested sample based SVPWM techniques achieve the voltage balancing of the DC‐link capacitors, while improving the harmonic performance of the drive. Specifically, one of the two proposed PWM schemes manages to clamp one of the inverters in every sampling time interval. Hence this scheme results in lowering the total harmonic distortion (THD) in the no‐load current in most of the operating range of the drive, resulting in lower ripple in the motor phase current, lower ohmic loss and reduced torque ripple. The performances of the proposed PWM techniques are assessed with the aid of simulation studies and are validated with the experimentation.