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Summary The four‐level open‐end winding induction motor (4‐L OEWIM) drive is constituted by two 2‐level voltage source inverters (VSIs), wherein their DC‐link voltages should be maintained in the ratio of 2:1. Owing to the unsymmetrical structure of the power circuit, the 4‐L OEWIM drive is plagued with the drawback of capacitor voltage imbalance. The DC‐link capacitor of one of the inverters, which is operated with the lower voltage level, that show the propensity of getting charged up by its higher voltage counterpart, belonging to the other inverter. In this article, two variants of space‐vector pulse width modulation (SVPWM) schemes are suggested for the 4‐L OEWIM drive. The suggested sample based SVPWM techniques achieve the voltage balancing of the DC‐link capacitors, while improving the harmonic performance of the drive. Specifically, one of the two proposed PWM schemes manages to clamp one of the inverters in every sampling time interval. Hence this scheme results in lowering the total harmonic distortion (THD) in the no‐load current in most of the operating range of the drive, resulting in lower ripple in the motor phase current, lower ohmic loss and reduced torque ripple. The performances of the proposed PWM techniques are assessed with the aid of simulation studies and are validated with the experimentation.

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Summary The dual‐inverter fed open‐end winding induction machine drive is a promising power circuit for medium‐voltage, high‐power industrial applications. This drive accomplishes 3‐level inversion using a couple of ordinary 2‐level voltage source inverters. Several PWM schemes were proposed for this drive to obtain a good harmonic performance. In this paper, an improvised space vector PWM (SVPWM) scheme is presented, which is named the phase clamped and alternate switched (PCAS) PWM strategy. This PWM scheme brings in a considerable reduction in the switching power loss in the dual‐inverter system. The PCAS‐SVPWM strategy switches only two phases of the switching inverter in any given sampling time period, unlike the other SVPWM schemes, wherein all the three phases of the switching inverter undergo a switching action. In addition, the proposed SVPWM achieves the waveform symmetries and reduces the common‐mode voltage. Simulation results suggest that this PWM scheme results in a reduction of the overall power loss, which is in the range of 4.5% to 11% across the entire range of modulation, depending upon the rating of the machine. The effectiveness of the proposed PCAS‐SVPWM scheme is assessed with simulation studies and is experimentally validated with laboratory prototype.

SummaryThis paper proposes a fault‐tolerant power converter for a voltage source inverter (VSI)‐driven permanent magnet brush‐less direct current (PM‐BLDC) motor drive, which is suitable for low‐power electric vehicle (EV) applications. With the proposed topology, it is possible to deliver rated power to the PM‐BLDC motor even after the incidence of either an open‐circuit fault (OCF) or a short‐circuit fault (SCF) in any one of the switches, which constitute the VSI. The proposed fault‐tolerant PM‐BLDC motor drive requires fewer additional sensors and components compared to the fault‐tolerant power converters, which are reported in the previous literature. Cost analysis, carried out for a 3‐kW motor drive, reveals that an additional cost of only 5% is added to the raw material cost of the traditional PM‐BLDC motor configuration to facilitate fault tolerance. The fault‐tolerant operation of the proposed power converter is experimentally verified with a low‐power laboratory prototype.